Senior IP Layout Engineer – DRAM & Analog Blocks

Micron Memory Malaysia Sdn Bhd; Boise (ID); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Paid time-off program

Job summary

Micron Technology in Boise, Idaho, is seeking a Layout Engineer to develop IP layouts for DRAM chips and collaborate with a global team to deliver high-quality designs. This role focuses on translating circuit concepts into efficient physical layouts while maintaining tight area and performance targets.

You will verify layouts with LVS/DRC/EM, guide sub-block layouts, and contribute to project management, coordinating with US, India, Japan, and other sites to ensure on-time, successful layout

Qualifications

• Experience performing physical layout using Cadence Virtuoso and similar tools.
• Familiarity with DRC, LVS, physical verification, and reliability checks.
• Ability to design high-performance layouts with area efficiency.
• Hands-on experience with analog layout blocks such as sensors and PLLs.

Responsibilities

• Design and development of IP layouts used in DRAM chips.
• Perform layout verification like LVS/DRC/EM, quality check and documentation.
• Deliver block-level layouts on time with acceptable quality.
• Guide and lead team-members in their execution of sub block-level layouts.
• Contribute to effective project-management.
• Communicate with engineering teams in US, India, Japan and other global teams to assure success.

Skills

Cadence Virtuoso

Physical layout

Layout verification

DRAM design

Analog layout

Job description

Micron Technology in Boise, Idaho, is seeking a Layout Engineer to develop IP layouts for DRAM chips and collaborate with a global team to deliver high-quality designs. This role focuses on translating circuit concepts into efficient physical layouts while maintaining tight area and performance targets.

You will verify layouts with LVS/DRC/EM, guide sub-block layouts, and contribute to project management, coordinating with US, India, Japan, and other sites to ensure on-time, successful layout