Engineering Director - Verification IP

Siemens EDA (Siemens Digital Industries Software); Austin (TX); On-site; USD 130,000 - 170,000; Full time

Benefits offered by this job

Competitive base salary

Bonus scheme

Generous holiday allowance

Pension

Private healthcare

Job summary

A global technology leader in Electronic Design Automation is seeking an experienced candidate for a role in Austin. This position requires over 15 years of expertise in RTL design and strong knowledge of SystemVerilog and UVM. The candidate will work alongside field engineers and customers to tackle deployment challenges and contribute to the development of verification IPs for cutting-edge technologies. A competitive salary and comprehensive benefits package are offered, reflecting the company's commitment to supporting its employees.

Qualifications

• 15+ years of experience in RTL design, IP/VIP development, verification, or emulation.
• Strong knowledge of SystemVerilog and UVM with experience in debugging and test plans.
• Understanding of bus protocols such as PCIe, CXL, USB, and Ethernet.

Responsibilities

• Work with field engineers and customers to resolve issues.
• Participate in the development of verification IPs for various interfaces.

Skills

SystemVerilog

UVM

RTL design

IP/VIP development

Debugging

Assertions

C/SystemC

Bus Protocols

Performance Metrics

Education

B.Tech/M.Tech in Electronics

Job description

Siemens EDA is a global technology leader in Electronic Design Automation software. Our tools enable companies worldwide to develop highly innovative electronic products faster and more cost‑effectively.

Responsibilities

• Role is based in Austin and involves working with teams that impact entire cities, countries, and the shape of future products.
• Work with field engineers (PEs) and account engineers (AEs) or directly with customers to deploy and resolve customer issues.
• Participate in development of comprehensive verification IPs for interfaces such as PCIe Gen5/Gen6, USB3.2, 400 GbE, DDR5, LPDDR5 and coherency protocols like CXL for use with Questa RTL simulation.

Qualifications

• B.Tech/M.Tech in Electronics or a related field from a reputed institute.
• 15+ years of working experience in RTL design, IP/VIP development, verification or emulation with industry leadership.
• Strong knowledge of SystemVerilog and UVM; experience with assertions, coverage, test plans, BFMs, debugging, loggers and trackers.
• Understanding of register layering and bus protocols such as PCIe, CXL, USB, Ethernet, Memory, CHI, etc.
• Experience with C/SystemC based tests is an added advantage.
• Knowledge of coherent and non‑coherent NOC, understanding of various components (CPU, GPU, display, network, device, memory).
• Familiarity with system‑level performance metrics such as latency, bandwidth and overall performance.

We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status or disability status. We are an equal‑opportunity employer and value diversity at our company.

We offer a comprehensive rewards package, including a competitive base salary, bonus scheme, generous holiday allowance, pension, and private healthcare.