Design Verification Engineer - Interface IP

Etched; Austin (TX); On-site; USD 150,000 - 275,000; Full time

Benefits offered by this job

Medical, dental, and vision benefits

Wellness benefits

Daily lunch + dinner

Unlimited compute budget

Job summary

Etched, based in Austin, seeks a Design Verification Engineer to join the Interface IP DV team. You will validate correctness and performance across the hardware-software stack, coordinating with architects, designers, and vendors to meet IP subsystem requirements.

The role emphasizes creativity, deep technical ability, and ownership of verification challenges in a fast-paced startup environment. You will interact with RTL, software, and emulation teams while spending time in our Austin office,

Qualifications

• 5+ years of design verification experience.
• Creativity in tackling complex verification challenges.
• Experience with SystemVerilog/UVM and scalable testbenches.

Responsibilities

• End to end ownership of one or more IP subsystems (PCIe, Ethernet, CPU, low power peripherals, sensors).
• Understand vendor IP configurations and coordinate with internal IP teams.
• Develop and maintain UVM/SystemVerilog verification environments for functional correctness and performance.
• Collaborate with integration and SoC DV teams to validate IP interactions within the chip architecture.
• Drive coverage closure and sign-off by defining metrics and analyzing gaps.

Skills

Design verification

SystemVerilog/UVM

IP/SoC interface

Hands-on debugging

Startup environment

Tools

UVM

SystemVerilog

Job description

About Etched

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

We are seeking a Design Verification Engineer to join our Interface IP DV team. You will work with architects, designers, and vendors to ensure that all our architecture requirements are met in the IP subsystems and interfaces being created, validate correctness and performance across the full hardware-software stack. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges.

Key Responsibilities

• End to end ownership of one or more of the following IP subsystems: PCIe, Ethernet, CPU (arc/arm), low power peripherals, sensors
• Understand vendor IP configurations and handle handshake with internal IP team
• Develop and maintain UVM/SystemVerilog-based verification environments to ensure functional correctness, performance, and compliance with IP specifications.
• Collaborate with integration and SoC DV teams to validate seamless interaction of external IPs within the broader chip architecture.
• Drive coverage closure and sign-off by defining metrics, analyzing gaps, and ensuring comprehensive verification across corner cases and stress scenarios.

You may be a good fit if you have

• 5+ years of design verification experience
• You enjoy digging deep into complex verification challenges and finding creative ways to expose corner-case bugs.
• You have hands-on experience with industry-standard verification methodologies like SystemVerilog/UVM and understand how to build scalable, reusable testbenches.
• You are comfortable working with standard IP interfaces and protocols such as PCIe, Ethernet, AXI/AMBA, or ARM/ARC CPUs.
• You thrive in a fast-paced startup environment and can take ownership of projects with minimal direction.
• You collaborate naturally with cross-functional teams — from RTL design to software and emulation — and can clearly communicate technical insights.

Strong Candidates May Also Have Experience With

• Experience handling vendors and integration of IP/VIP’s
• UVM/System Verilog

Benefits

• Medical, dental, and vision packages with generous premium coverage
  • $500 per month credit for waiving medical benefits
• Various wellness benefits covering fitness, mental health, and more
• Daily lunch + dinner in our office
• Unlimited compute budget subject to ROI justification

How We’re Different

Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system. Our addressable market is the entirety of inference, unlike many of our competitors. We greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.

This role is based in our Austin office, with regular time spent working alongside the team in San Jose. During the first quarter, expect to spend approximately two weeks per month at our San Jose headquarters to ramp quickly. After that, this shifts to roughly one week per month for ongoing collaboration.

Compensation Range: $150K - $275K