SoC Timing & STA Design Engineer – Tapeout Focus

Apple Inc.; San Jose (CA); Hybrid; USD 129,000 - 195,000; Full time

Job summary

Apple Inc. is seeking a SoC Physical Design Engineer focused on STA/Timing to drive the timing closure from netlist to tapeout for a high-performance SoC.

You will debug constraints, develop timing infrastructures, and create ECOs while collaborating with design and PD teams to address issues and ensure optimal performance. Strong scripting in Perl/TCL and SPICE familiarity preferred.

Qualifications

• Bachelor's degree with 0+ years industry experience.
• Experience with STA.
• Experience with noise, crosstalk, and/or OCV effects.

Responsibilities

• Work with design teams to understand and debug constraints and facilitate logic changes to improve timing.
• Work with the Physical Design team, highlighting issues and best practices.
• Help create timing ECO’s for project tapeout.
• Create and maintain scripts and methodologies for analysis and runs.
• Create documentation and help with guidelines/specs.
• Deep analysis of timing paths to identify key issues.
• Implement timing infrastructure.

Skills

STA/Timing

Timing closure

Perl

TCL

Noise analysis

Education

Bachelor's degree

Tools

SPICE models

Job description

Apple Inc. is seeking a SoC Physical Design Engineer focused on STA/Timing to drive the timing closure from netlist to tapeout for a high-performance SoC.

You will debug constraints, develop timing infrastructures, and create ECOs while collaborating with design and PD teams to address issues and ensure optimal performance. Strong scripting in Perl/TCL and SPICE familiarity preferred.