SoC Timing & Signoff Engineer - Full-Chip STA Expert

Google; Jasper (AL); On-site; USD 138,000 - 197,000; Full time

Job summary

Google is seeking a Static Timing Analysis Engineer to own full-chip STA for SoCs in Mountain View, CA. You will implement timing signoff, optimize clock tree, and ensure energy and area goals.

Mid-level role requires 4 years of silicon timing experience, proficiency with PrimeTime/Tempus, and scripting in Tcl or Perl. You will collaborate with design, verification, and layout teams to drive silicon delivery.

Qualifications

• Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
• 4 years of technical experience in silicon timing closure and chip integration.
• Experience in one or more static timing tools (e.g., PrimeTime, Tempus).
• Experience with STA signoff constraint authoring for full-chip level, tapeout signoff requirements, checklists, and automation.
• Experience delivering silicon.

Responsibilities

• Deliver system-on-chip (SoC) Static Timing Analysis.
• Define SoC timing signoff process corners, derates, uncertainties and their tradeoffs.
• Drive clock tree jitter and implementation for SoCs to achieve best energy, performance, and area.
• Execute full chip timing constraint validation and timing signoff checklist criteria, perform full chip Static Timing Analysis (STA) and timing ECO creation, and oversee final timing signoff for SoCs.

Skills

Silicon timing closure

Scripting Tcl/Perl

Clock tree optimization

Education

Bachelor's degree in Electrical Engineering or Computer Science

Master's degree in Electrical Engineering or Computer Science

Tools

PrimeTime

Tempus

Job description

Google is seeking a Static Timing Analysis Engineer to own full-chip STA for SoCs in Mountain View, CA. You will implement timing signoff, optimize clock tree, and ensure energy and area goals.

Mid-level role requires 4 years of silicon timing experience, proficiency with PrimeTime/Tempus, and scripting in Tcl or Perl. You will collaborate with design, verification, and layout teams to drive silicon delivery.