SoC Static Timing Engineer — Full-Chip Signoff

Google; Mountain View (CA); On-site; USD 163,000 - 236,000; Full time

Job summary

Google seeks an experienced engineer to lead SoC Static Timing Analysis for complex silicon. You will define timing signoff, manage constraints, and optimize clocking for energy, performance, and area across full-chip designs.

The role emphasizes delivering high-complexity silicon, with experience in PrimeTime/Tempus and STA signoff for tapeouts, and collaboration with hardware teams to meet aggressive schedules.

Qualifications

• Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
• 8 years of technical experience in silicon timing closure and chip integration.
• Experience in one or more static timing tools (e.g., PrimeTime, Tempus).
• Experience with STA signoff constraint authoring for full-chip level, tapeout signoff requirements, checklists, and associated automation.
• Experience delivering silicon.

Responsibilities

• Be responsible for delivering system-on-chip (SoC) Static Timing Analysis (STA).
• Define SoC timing signoff process corners, derates, uncertainties and their tradeoffs.
• Drive clock tree Jitter and implementation for SoCs to achieve best energy, performance and area.
• Manage full chip timing constraint validation, timing signoff checklist criteria, perform full chip STA, timing ECO creation and oversee final timing signoff for SoC’s.

Skills

ASIC design flows

Device physics knowledge

Deliver high complexity silicon

Tcl/Perl scripting

Education

Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience

Master's degree in Electrical Engineering, Computer Science, or a related field

Tools

PrimeTime

Tempus

STA signoff constraints tooling

Job description

Google seeks an experienced engineer to lead SoC Static Timing Analysis for complex silicon. You will define timing signoff, manage constraints, and optimize clocking for energy, performance, and area across full-chip designs.

The role emphasizes delivering high-complexity silicon, with experience in PrimeTime/Tempus and STA signoff for tapeouts, and collaboration with hardware teams to meet aggressive schedules.