SoC RTL Design Intern – Memory SSDs (San Jose)

SK Hynix Memory Solution; San Jose (CA); On-site; USD 48,000 - 62,000; Full time

Benefits offered by this job

6-month internship

On-site in San Jose

Job summary

SK hynix memory solutions America invites you to join the SoC Design Team as an intern, delivering RTL design and contributing to high-performance SSD controller projects.

This 6-month, full-time internship (40 hours/week) starts immediately in San Jose, CA. You will collaborate across Verification, Silicon Validation, and Firmware teams to ensure design quality and timely tapeout readiness.

Qualifications

• Currently enrolled in BS/MS/PhD program in Electrical Engineering, Computer Engineering, or related field.
• Proficiency in logic design and micro-architecture; RTL coding in Verilog and/or SystemVerilog language.
• Advanced coursework or experience in digital logic design, verification methodologies, and related protocols (AMBA, PCIe, NAND, DDR).
• Scripting skills (Python, Perl, TCL) and Linux command-line experiences.
• Strong problem-solving and communication skills.
• Proficiency in AI tools to generate synthesizable and functional RTL code.

Responsibilities

• RTL design (Verilog/SystemVerilog) for IP based on existing module or new specifications.
• Collaborate with Design Verification, Silicon Validation, and Firmware teams to ensure design quality.

Skills

RTL design

Verilog/SystemVerilog

Micro-architecture

Python scripting

Education

BS/MS/PhD in Electrical Engineering or related field

Tools

Verilog

SystemVerilog

Linux command-line

Job description

SK hynix memory solutions America invites you to join the SoC Design Team as an intern, delivering RTL design and contributing to high-performance SSD controller projects.

This 6-month, full-time internship (40 hours/week) starts immediately in San Jose, CA. You will collaborate across Verification, Silicon Validation, and Firmware teams to ensure design quality and timely tapeout readiness.