SoC Power & Limits Lead

Google; Mountain View (CA); On-site; USD 240,000 - 333,000; Full time

Benefits offered by this job

Equity

Bonus target

Benefits

Job summary

Google is seeking a SoC Limits Management Lead to define how next‑generation systems balance performance with power and reliability. You will bridge hardware IP, system software, and product requirements to design a holistic limits management subsystem for scalable silicon health.

You will lead cross‑functional teams, standardize mitigation features such as power telemetry and droop detectors, and shape the long‑term evolution of sensing IPs to address rising currents.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
• 15 years of industry experience in Power Management or Low‑Power Design/Methodology.
• Experience navigating the full product delivery cycle, from initial architecture definition through to post‑silicon productization.
• Experience with low‑power architectures and advanced power optimization techniques.

Responsibilities

• Define the SoC limits management by integrating hardware triggers, firmware policies, and software mitigations to protect silicon health.
• Lead cross‑functional teams to standardize critical mitigation features, including Power Telemetry, Estimators, and Droop Detectors, across all IP and hardware blocks.
• Drive the long‑term evolution of Sensing IPs (Voltage, Current, Temperature) and trigger mechanisms to address escalating current densities and industry trends.
• Design real‑time telemetry requirements to monitor silicon behavior and define performance‑impact profiles for various mitigation strategies.
• Drive organizational consensus on feature ROI and oversee Post‑Silicon Validation to ensure physical silicon behavior aligns with architectural intent.

Skills

Power management

Low-power design

Architecture definition

Cross-functional leadership

System power

Education

Bachelor's degree

Job description

Google is seeking a SoC Limits Management Lead to define how next‑generation systems balance performance with power and reliability. You will bridge hardware IP, system software, and product requirements to design a holistic limits management subsystem for scalable silicon health.

You will lead cross‑functional teams, standardize mitigation features such as power telemetry and droop detectors, and shape the long‑term evolution of sensing IPs to address rising currents.