Early‑Career SOC Limits Architect - Power & Telemetry

QUALCOMM, Inc.

San Diego (CA)

On-site

USD 146,000 - 218,000

Full time

14 days+

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Job summary

Qualcomm Technologies, Inc. seeks a SoC Limits Management Architect for the HW power team. You will define how next-generation systems balance high performance with physical, electrical and thermal limits, bridging hardware IP, software, and product requirements.

You will lead cross-functional teams to standardize mitigation features and guide product definition through early lifecycle involvement, with a focus on telemetry and sensing IP evolution.

Qualifications

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
  • MS or PhD in Electronics or Computer Engineering, or equivalent with focus on computer architecture and power/performance analysis.
  • 6+ years of ASIC design, verification, validation, integration, or related work experience (5+ years if Master’s; 4+ years if PhD).

Responsibilities

  • Define the SoC limits management by integrating hardware triggers, firmware policies, and software mitigations to protect silicon health.
  • Lead cross-functional teams to standardize critical mitigation features, including Power Telemetry, Estimators, and Droop Detectors.
  • Drive the long-term evolution of Sensing IPs (Voltage, Current, Temperature) and trigger mechanisms.
  • Design real-time telemetry requirements to monitor silicon behavior and define performance-impact profiles.
  • Oversee Post-Silicon Validation to ensure alignment with architectural intent.
  • Help with post-silicon power correlation to match pre-silicon models with actual silicon measurements.

Skills

C/C++ development
Python
FW prototyping

Education

Bachelors in ECE/CS
MS/PhD in Electronics/CE

Job description

Qualcomm Technologies, Inc. seeks a SoC Limits Management Architect for the HW power team. You will define how next-generation systems balance high performance with physical, electrical and thermal limits, bridging hardware IP, software, and product requirements.

You will lead cross-functional teams to standardize mitigation features and guide product definition through early lifecycle involvement, with a focus on telemetry and sensing IP evolution.

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