SoC Limits Management Lead

Google; Mountain View (CA); On-site; USD 240,000 - 333,000; Full time

Benefits offered by this job

Equity

Bonus target

Benefits

Job summary

Google is seeking a SoC Limits Management Lead to define how next‑generation systems balance performance with power and reliability. You will bridge hardware IP, system software, and product requirements to design a holistic limits management subsystem for scalable silicon health.

You will lead cross‑functional teams, standardize mitigation features such as power telemetry and droop detectors, and shape the long‑term evolution of sensing IPs to address rising currents.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
• 15 years of industry experience in Power Management or Low‑Power Design/Methodology.
• Experience navigating the full product delivery cycle, from initial architecture definition through to post‑silicon productization.
• Experience with low‑power architectures and advanced power optimization techniques.

Responsibilities

• Define the SoC limits management by integrating hardware triggers, firmware policies, and software mitigations to protect silicon health.
• Lead cross‑functional teams to standardize critical mitigation features, including Power Telemetry, Estimators, and Droop Detectors, across all IP and hardware blocks.
• Drive the long‑term evolution of Sensing IPs (Voltage, Current, Temperature) and trigger mechanisms to address escalating current densities and industry trends.
• Design real‑time telemetry requirements to monitor silicon behavior and define performance‑impact profiles for various mitigation strategies.
• Drive organizational consensus on feature ROI and oversee Post‑Silicon Validation to ensure physical silicon behavior aligns with architectural intent.

Skills

Power management

Low-power design

Architecture definition

Cross-functional leadership

System power

Education

Bachelor's degree

Job description

In most instances, this position requires in‑person interviews as part of the hiring process.

Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Mountain View, CA, USA; San Diego, CA, USA.

Minimum qualifications:

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
• 15 years of industry experience in Power Management or Low‑Power Design/Methodology.
• Experience navigating the full product delivery cycle, from initial architecture definition through to post‑silicon productization.
• Experience with low‑power architectures and advanced power optimization techniques.

Preferred qualifications:

• MS or PhD in Electronics or Computer Engineering, or equivalent, with a focus on computer architecture and power/performance analysis.
• Experience in peak power management, in‑rush current, PDN droop detection and mitigation, adaptive clock distribution, aging and process monitors, power aware floorplanning, battery technology, concurrency management and thermal management.
• Exceptional leadership and influencing skills, with an ability to influence cross‑functional roadmaps and drive ROI‑based technical decisions.

About The Job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google’s direct‑to‑consumer products. You’ll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a SoC Limits Management Lead in the System Power and Performance team, you will be responsible for defining how our next‑generation systems balance high performance against physical and electrical constraints. You will bridge the gap between hardware IP, system software, and product requirements to design a holistic “Limits Management” subsystem. Your work ensures our SoCs deliver maximum performance under peak current constraints, while maintaining long‑term reliability and stability.

Google’s mission is to organize the world’s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people’s lives better through technology.

Individual pay is determined by factors including job‑related skills, experience, and relevant education or training.

US: $240000 - $333000 (USD) + 25% bonus target + equity + benefits

Responsibilities

Learn more about benefits at Google.

• Define the SoC limits management by integrating hardware triggers, firmware policies, and software mitigations to protect silicon health.
• Lead cross‑functional teams to standardize critical mitigation features, including Power Telemetry, Estimators, and Droop Detectors, across all IP and hardware blocks.
• Drive the long‑term evolution of Sensing IPs (Voltage, Current, Temperature) and trigger mechanisms to address escalating current densities and industry trends.
• Design real‑time telemetry requirements to monitor silicon behavior and define performance‑impact profiles for various mitigation strategies.
• Drive organizational consensus on feature return on investment (ROI) and oversee Post‑Silicon Validation to ensure physical silicon behavior aligns with architectural intent.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google’s EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.