SoC Limits & Power Architect: Real-Time Telemetry

QUALCOMM, Inc.; San Diego (CA); Sur place; USD 146 000 - 218 000; Plein temps

Avantages offerts par ce poste

Discretionary bonus

RSU grants

Benefits package

Résumé du poste

Qualcomm Technologies, Inc. seeks a SoC Limits Management Architect on the HW power team to balance high performance against physical, electrical and thermal constraints.

You will bridge hardware IP, system software, and product requirements to design a holistic Limits Management architecture and guide product definition through early life cycle involvement. You will lead cross-functional teams to standardize mitigation features, drive evolution of sensing IPs and implement telemetry to monitor

Qualifications

• Bachelor's degree in Science, Engineering, or related field with 4+ years of ASIC design/verification experience.
• MS or PhD with focus on computer architecture and power/performance analysis.
• 6+ years of ASIC design, verification, validation, integration, or related work experience (5+ years if Master’s; 4+ years if PhD).
• Experience with power management and low-power design methodologies.
• Strong C/C++ development skills for architectural modeling and FW prototyping, alongside Python for data analysis, performance profiling, and workflow automation.

Responsabilités

• Define the SoC limits management by integrating hardware triggers, firmware policies, and software mitigations to protect silicon health.
• Lead cross-functional teams to standardize critical mitigation features across all IP and hardware blocks.
• Drive the long-term evolution of Sensing IPs (Voltage, Current, Temperature) and trigger mechanisms.
• Design real-time telemetry requirements to monitor silicon behavior and define performance-impact profiles for various mitigation strategies.
• Drive organizational consensus on feature ROI and oversee Post-Silicon Validation to ensure alignment with architectural intent.
• Help with post silicon power correlation to match with pre-silicon power models and simulations with actual physical measurements taken from silicon.

Connaissances

C/C++ development

Python

Architectural modeling

FW prototyping

Formation

Bachelor's degree

Master's degree

PhD

Description du poste

Qualcomm Technologies, Inc. seeks a SoC Limits Management Architect on the HW power team to balance high performance against physical, electrical and thermal constraints.

You will bridge hardware IP, system software, and product requirements to design a holistic Limits Management architecture and guide product definition through early life cycle involvement. You will lead cross-functional teams to standardize mitigation features, drive evolution of sensing IPs and implement telemetry to monitor