SoC Limits Lead — Power & Performance Architect

Google LLC; Mountain View, San Diego (CA, CA); On-site; USD 240,000 - 333,000; Full time

Job summary

Google LLC in Mountain View, CA is seeking a SoC Limits Management Lead to balance high performance with physical and electrical constraints across next-generation systems. You will bridge hardware IP, system software, and product requirements to design a holistic limits management subsystem for maximum performance under peak current.

The role leads cross-functional teams, defines telemetry needs, and guides post-silicon validation to ensure the intended architectural outcomes while delivering

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
• 15 years of industry experience in Power Management or Low-Power Design/Methodology.
• Experience navigating the full product delivery cycle, from initial architecture definition through to post-silicon productization.
• Experience with low-power architectures and advanced power optimization techniques.

Responsibilities

• Define SoC limits management by integrating hardware triggers, firmware policies, and software mitigations to protect silicon health.
• Lead cross-functional teams to standardize mitigation features across IP and hardware blocks.
• Drive evolution of Sensing IPs (Voltage, Current, Temperature) and trigger mechanisms for high current densities.
• Design real-time telemetry requirements to monitor silicon behavior and define performance-impact profiles.
• Drive ROI alignment and oversee Post-Silicon Validation to ensure silicon behavior matches architecture.

Skills

Power management

Low-power design

Architecture definition

Product lifecycle

Cross-functional leadership

Education

Bachelor's degree

Job description

Google LLC in Mountain View, CA is seeking a SoC Limits Management Lead to balance high performance with physical and electrical constraints across next-generation systems. You will bridge hardware IP, system software, and product requirements to design a holistic limits management subsystem for maximum performance under peak current.

The role leads cross-functional teams, defines telemetry needs, and guides post-silicon validation to ensure the intended architectural outcomes while delivering