SoC Physical Design Engineer, PnR

Apple Inc.; San Diego (CA); On-site; USD 142,300 - 263,300; Full time

Benefits offered by this job

RSU awards

Stock purchase at discount

Relocation assistance

Medical and dental coverage

Retirement benefits

Employee discounts

Tuition reimbursement

Job summary

Apple is seeking a highly experienced engineer to oversee physical implementation of design partitions for a complex SOC, translating from netlist to tapeout. You will collaborate with logic design to integrate partition architecture early in the cycle and ensure adherence to schedules and performance goals.

Responsibilities include netlist-to-GDS2 implementation, timing and physical verification, and driving signoff closure for partitions, while resolving design and flow issues to push

Qualifications

• BS degree and 3+ years of relevant industry experience.
• Experience with partition level P&R implementation.
• Experience with floorplanning, clock and power distribution, timing closure, physical verification, electrical verification.

Responsibilities

• Implement partitions from netlist to GDS2 with schedule and design goals.
• Drive timing, physical and electrical verification and signoff closure for partitions.
• Resolve and improve physical design issues and drive execution.

Skills

Partition level P&R

Floorplanning

Clock and power distribution

Timing closure

Physical verification

Electrical verification

Education

Bachelor's degree

Job description

Overview

You will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process technology.

Responsibilities

• Work with the logic design team to understand partition architecture and drive physical aspects early in the design cycle.
• Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals.
• Timing, physical and electrical verification, and driving the signoff closure for the partitions.
• Resolve and improve design and flow issues related to physical design, identify potential solutions, and drive execution.

Minimum Qualifications

• Minimum BS and 3+ years of relevant industry experience.
• Experience with partition level P&R implementation.
• Experience with one or more of the following: floorplanning, clock and power distribution, timing closure, physical verification, electrical verification.

Preferred Qualifications

• Ability to adhere to stringent schedule and die size requirements.
• Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHz.
• Experience with sub 10nm tech nodes.
• Experience with industry standard tools, understanding their capabilities and underlying algorithms.
• Experience with physical design construction and analysis flows and methodology.

Compensation and Benefits

Base pay range for this role is between $142,300 and $263,300, depending on skills, qualifications, experience, and location.

Apple employees are also eligible for discretionary restricted stock unit awards, can purchase Apple stock at a discount, and may receive discretionary bonuses or commission payments as well as relocation. Benefits include comprehensive medical and dental coverage, retirement benefits, discounted products and free services, and reimbursement for certain educational expenses—including tuition.

Equal Opportunity Employer

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics.

Accessibility

At Apple, we believe accessibility is a fundamental human right. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.

Learn about reasonable accommodations for job applicants.