SoC Physical Design Engineer, PnR

Apple Inc.; United States; On-site; USD 150,000 - 230,000; Full time

Job summary

Apple Inc. is seeking an experienced Physical Design engineer to own partition-level implementation for a complex SOC in Beaverton, Oregon. You will partner with logic design to translate partitions from netlist to GDS2, drive timing, power, and sign-off, and push die-size and schedule goals.

The role requires a BS with 10+ years in SOC design, expertise in floorplanning, clock and power distribution, timing closure, and verification flows. MS degree preferred.

Qualifications

• BS in Electrical Engineering or related field.
• 10+ years of relevant industry experience.
• Experience with large SOC designs (>20M gates) and >1 GHz frequencies.

Responsibilities

• Drive physical implementation of partitions from netlist to tapeout.
• Perform timing, physical, and electrical verification and drive sign-off.
• Optimize P&R partitions for Power/Performance/Area.
• Collaborate with logic design on partition architecture and flow.
• Resolve and improve design issues in physical design and flow.

Skills

Partition-level P&R

Floorplanning

Timing closure

Physical verification

Electrical verification

Power distribution

Clock distribution

SOC design

CAD tools

Process variations

Education

Bachelor's degree in Electrical Engineering or related field

MS in Electrical/Electronics/Computer Engineering

Tools

Cadence

Synopsys

Mentor Graphics

DA/Verification tools

Job description

In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process technology.

Description

• Work with the logic design team to understand partition architecture and drive physical aspects early in the design cycle.
• Complete netlist to GDS2 implementation for partitions meeting schedule and design goals.
• Perform timing, physical, and electrical verification, and drive sign‑off closure for the partitions.
• Resolve and improve design and flow issues related to physical design, identify potential solutions, and drive execution.
• Drive optimization of PnR partitions to achieve the best Power/Performance/Area.

Minimum Qualifications

• Minimum BS and 10+ years of relevant industry experience.

Preferred Qualifications

• MS in Electrical/Electronics/Computer Engineering or related field.
• Experience with partition‑level P&R implementation including floorplanning, clock and power distribution, timing closure, and physical and electrical verification.
• Experience with physical design construction and analysis flows and methodology.
• Experience with large SOC designs (>20M gates) with frequencies in excess of 1 GHz.
• Familiar with various process‑related design issues including Design for Yield, Manufacturability, and multi‑VT strategies.
• Experience with industry standard tools, understanding their capabilities and underlying algorithms.
• Experience with typical SOC issues such as multiple voltage and clock domains and mixed‑signal block integration.
• From a CAD perspective, experience with floorplanning tools, P&R flows, global timing verification, and physical design verification flows.
• Ability to adhere to stringent schedule and die‑size requirements.

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