SoC Physical Design Engineer, PnR

Apple Inc.; Beaverton (OR); On-site; USD 120,000 - 170,000; Full time

Job summary

Apple Inc. in Beaverton, Oregon is seeking a skilled physical design engineer to drive partition-level implementation for a complex SOC. You will collaborate with the logic team from early architecture through netlist to GDS2, ensuring timely delivery and signoff.

The role requires sub-10nm experience, large SOC work, and robust proficiency with standard EDA tools to meet aggressive die-size and performance goals.

Qualifications

• BS degree required and 3+ years of hardware experience.
• Partition level P&R experience including floorplanning.
• Clock and power distribution experience.
• Timing closure and physical verification experience.
• Experience with large SOC designs (>20M gates) at frequencies >1GHz.
• Experience with sub-10nm technology nodes.
• Familiar with industry-standard EDA tools.

Responsibilities

• Collaborate with logic design to define partition architecture early.
• Implement netlist to GDS2 for partitions meeting schedule.
• Perform timing, physical and electrical verification and drive signoff.
• Identify and fix physical design issues and drive execution.

Skills

Partition P&R

Floorplanning

Timing closure

Physical verification

Electrical verification

SOC design

Sub-10nm

EDA tools

Education

Bachelor's degree

Tools

Industry standard tools

Job description

Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hardworking people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product!In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC utilizing innovative process technology.

Description

• Work with the logic design team to understand partition architecture and drive physical aspects early in the design cycle.
• Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals.
• Timing, physical and electrical verification, and driving the signoff closure for the partitions.
• Resolve and improve design and flow issues related to physical design, identify potential solutions, and drive execution.

Minimum Qualifications

• Minimum BS and 3+ years of relevant industry experience.

Preferred Qualifications

• Experience with partition level P&R implementation including floorplanning, clock and power distribution, timing closure, physical and electrical verification.
• Experience with physical design construction and analysis flows and methodology.
• Ability to adhere to stringent schedule and die size requirements.
• Experience with large SOC designs (>20M gates) with frequencies in excess of 1GHZ.
• Experience with sub 10nm tech nodes.
• Experience with industry standard tools, understanding their capabilities and underlying algorithms.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant

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