SoC Physical Design Engineer – Tapeout & Verification

Socket.dev; San Jose (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

Apple's Silicon Technologies group seeks a dedicated physical design verification engineer to help ensure high-performance SoCs meet signoff deadlines. You will perform LVS, DRC, DFM/DFY and lithography checks, collaborate with CAD/Technology and implementation teams, and drive tapeout signoff and schedules across cross-functional groups in a fast-paced environment.

Experience with pad-ring, bump, RDL, and floorplanning is a plus; strong scripting skills are essential to debug flows and automate

Qualifications

• Strong knowledge of physical verification flows and methodology.
• Knowledge of all aspects of ASIC physical design.
• Scripting skills to debug flow related issues and enhancements.
• Experience with industry-standard tools for physical verification (Mentor Calibre, Synopsys ICV).

Responsibilities

• Perform LVS, DRC, DFM/DFY, and lithography checks at chip and block level.
• Collaborate with CAD/Technology teams for flow bring up and validation.
• Drive signoff closure for tapeout and lead schedules.
• Work on padring, bump, RDL design with package and floorplan teams.

Skills

Physical verification

ASIC physical design

Scripting

Tools

Mentor Calibre

Synopsys ICV

Job description

Apple's Silicon Technologies group seeks a dedicated physical design verification engineer to help ensure high-performance SoCs meet signoff deadlines. You will perform LVS, DRC, DFM/DFY and lithography checks, collaborate with CAD/Technology and implementation teams, and drive tapeout signoff and schedules across cross-functional groups in a fast-paced environment.

Experience with pad-ring, bump, RDL, and floorplanning is a plus; strong scripting skills are essential to debug flows and automate