SoC Physical Design Methodology Engineer

Apple Inc.; Beaverton (OR); On-site; USD 130,000 - 160,000; Full time

Job summary

Apple Inc. is seeking a SoC Physical Design Methodology Engineer in Beaverton, Oregon. The role involves designing high-performance processors and ensuring that Apple products manage tasks seamlessly.

The ideal candidate has a BS degree and over 10 years of industry experience in physical design, with strong skills in physical verification flows, scripting, and industry-standard tools. Join Apple to thrive in an inclusive environment that values diversity.

Qualifications

• 10+ years of relevant experience in physical design.
• Strong knowledge of ASIC physical design and verification checks.
• Experience with DRC, LVS, ESD, and macro placement design.

Responsibilities

• Perform physical verification checks at chip and block level.
• Collaborate with CAD/Technology teams for validation.
• Lead schedules and support engineering efforts.

Skills

Physical verification flows

Full-chip integration methodology

Scripting in perl/python/tcl

Industry standard tools

Education

BS and 10+ years of relevant industry experience

Tools

Mentor Calibre

Synopsys ICV

Job description

SoC Physical Design Methodology Engineer

As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions.

Description

• Perform various types of physical verification checks such as LVS, DRC, design-for-manufacturing & design-for-yield, and lithography at the chip and block level.
• Collaborate with the CAD/Technology teams for flow bring up and validation, work directly with the implementation team during the entire chip design cycle to drive signoff closure for tapeout.
• Lead schedules and support cross‑functional engineering efforts.
• Work on padring, bump, RDL design, and work with the package and floorplan teams.

Minimum Qualifications

• BS and 10+ years of relevant industry experience.

Preferred Qualifications

• Experienced with physical verification flows such as DRC/LVS/ANT/HVDRC signoff flows and full‑chip integration methodology.
• Experience with ESD and macro placement design guidelines, digital and analog mixed‑signal back‑end verification checks and methodology.
• Knowledge of all aspects of ASIC physical design and physical verification checks for hierarchical designs including full‑chip flows.
• Scripting skills perl/python/tcl to debug flow related issues and automate checks.
• Experienced in industry standard tools used for physical verification such as Mentor Calibre, Synopsys ICV, etc.
• Tapeout experience with a track record of successful signoffs.
• Layout design experience is a plus.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant.

At Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here — in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.

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