SoC Physical Design Methodology Engineer

Apple Inc.; San Jose (CA); On-site; USD 150,000 - 210,000; Full time

Job summary

Apple Inc. in San Jose, CA is seeking a SoC Physical Design Methodology Engineer to perform physical verification at chip and block levels and to drive tapeout signoffs.

You will collaborate with CAD/Technology groups, lead schedule cadence, and handle padring, bump, and RDL design in close coordination with package and floorplan teams. A BS with 10+ years of experience is required.

Qualifications

• BS and 10+ years of relevant industry experience.
• Experience with ASIC physical design and full-chip flows.
• Familiarity with design-for-manufacturing & design-for-yield

Responsibilities

• Perform physical verification checks at chip and block levels (LVS/DRC, etc.).
• Collaborate with CAD/Technology teams for flow bring-up and validation.
• Drive signoff closure for tapeout with cross-functional teams.
• Lead padring, bump, and RDL design activities with package/floorplan teams.

Skills

DRC/LVS flows

ANT/HVDRC signoff

ESD & macro placement guidance

back-end verification checks

Python/Perl/Tcl scripting

Calibre/ICV tooling

Tapeout signoffs

Layout Experience

Education

Bachelor's degree in Electrical Engineering or related field

Tools

Mentor Calibre

Synopsys ICV

Job description

SoC Physical Design Methodology Engineer

At Apple, we work every single day to craft products that enrich people's lives! Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining our group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, we will enable our customers to do all the things they love with their devices! In this highly visible role, you will be a part of a critical team responsible for physical verification of an SOC.

Description

As a member of our physical design team, you will perform various types of physical verification checks (such as LVS, DRC, design-for-manufacturing & design-for-yield, and lithography) at the chip and block level.

You will collaborate with the CAD/Technology teams for flow bring up and validation. We work directly with the implementation team during the entire chip design cycle to drive signoff closure for tapeout.

You will lead schedules and support cross-functional engineering efforts.

You will work on padring, bump, RDL design, and working with the package and floorplan teams.

Minimum Qualifications

• BS and 10+ years of relevant industry experience.

Preferred Qualifications

• Experienced with physical verification flows such as DRC/LVS/ANT/HVDRC signoff flows and full-chip integration methodology
• Experience with ESD and macro placement design guidelines, digital and analog mixed signal back-end verification checks and methodology
• Knowledge of all aspects of ASIC physical design and physical verification checks for hierarchical designs including full-chip flows
• Scripting skills perl/python/tcl to debug flow related issues and automate checks
• Experienced in industry standard tools used for physical verification such as Mentor Calibre, Synopsys ICV, etc.
• Tapeout experience with a track record of successful signoffs
• Layout design experience is a plus

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant

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Apple accepts applications to this posting on an ongoing basis.