Physical Design Engineer

Socket.dev; San Jose (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

Apple's Silicon Technologies group seeks a dedicated physical design verification engineer to help ensure high-performance SoCs meet signoff deadlines. You will perform LVS, DRC, DFM/DFY and lithography checks, collaborate with CAD/Technology and implementation teams, and drive tapeout signoff and schedules across cross-functional groups in a fast-paced environment.

Experience with pad-ring, bump, RDL, and floorplanning is a plus; strong scripting skills are essential to debug flows and automate

Qualifications

• Strong knowledge of physical verification flows and methodology.
• Knowledge of all aspects of ASIC physical design.
• Scripting skills to debug flow related issues and enhancements.
• Experience with industry-standard tools for physical verification (Mentor Calibre, Synopsys ICV).

Responsibilities

• Perform LVS, DRC, DFM/DFY, and lithography checks at chip and block level.
• Collaborate with CAD/Technology teams for flow bring up and validation.
• Drive signoff closure for tapeout and lead schedules.
• Work on padring, bump, RDL design with package and floorplan teams.

Skills

Physical verification

ASIC physical design

Scripting

Tools

Mentor Calibre

Synopsys ICV

Job description

At Apple, we work every single day to craft products that enrich people's lives! Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you’ll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You’ll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining our group means you’ll be responsible for crafting and building the technology that fuels Apple’s devices. Together, we will enable our customers to do all the things they love with their devices! In this highly visible role, you will be a part of a critical team responsible for physical verification of an SOC.

Description

As a member of our physical design team, you will perform various types of physical verification checks (such as LVS, DRC, design-for-manufacturing & design-for-yield, and lithography) at the chip and block level. You'll collaborate with the CAD/Technology teams for flow bring up and validation. We work directly with the implementation team during the entire chip design cycle to drive signoff closure for tapeout. You will lead schedules and support cross-functional engineering efforts. You'll work on padring, bump, RDL design, and working with the package and floorplan teams.

Minimum Qualifications

Strong knowledge of physical verification flows and methodology.

Knowledge of all aspects of ASIC physical design.

Scripting skills to debug flow related issues and make enhancements as appropriate.

Experienced in industry standard tools used for physical verification such as Mentor Calibre, Synopsys ICV, etc.

Real chip tapeout experience with a track record of successful signoff.

Preferred Qualifications

We would like you to have 1-3 years of physical design experience, with emphasis on physical verification.

Layout design background and experience a plus.