SoC Physical Design Engineer: RTL to Tapeout

Cypress HCM; Folsom (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

Cypress HCM in California seeks a proficient SoC Physical Design Engineer to translate RTL and netlists into optimized physical implementations. You will work with engineering teams to meet timing, power, and area goals using state-of-the-art EDA tools and automation scripts.

The role covers floorplanning, power grid design, placement, clock tree synthesis, routing, and rigorous verification to ensure successful tapeouts and manufacturability.

Responsibilities

• Develops and implements physical design solutions for SoC devices from RTL, netlists, and design constraints provided by engineering teams.
• Work may be completed through the use of EDA tools, automation scripts, and other computerized design equipment.
• Performs floorplanning, power grid design, placement, clock tree synthesis, routing, timing closure, and physical verification.
• Analyzes design quality, identifies implementation issues, and verifies completed layouts meet performance, power, area, and manufacturability requirements.
• May review physical design methodologies, validate implementation flows, and support tapeout activities.

Job description

Cypress HCM in California seeks a proficient SoC Physical Design Engineer to translate RTL and netlists into optimized physical implementations. You will work with engineering teams to meet timing, power, and area goals using state-of-the-art EDA tools and automation scripts.

The role covers floorplanning, power grid design, placement, clock tree synthesis, routing, and rigorous verification to ensure successful tapeouts and manufacturability.