SOC Physical Design Engineer: Power, Timing & Tape-out

Apple Inc.; Austin (TX); On-site; USD 140,000 - 190,000; Full time

Job summary

Apple Inc. in Austin, Texas is seeking a seasoned physical design engineer to implement System-On-Chip blocks from netlist through tape-out in advanced nodes.

You will collaborate with RTL teams to optimize placement, clock distribution and power integrity, drive design methodologies, and analyze STA/DRC/LVS reports. The role emphasizes automation, scripting, and continuous improvement of block construction recipes to reduce area, power, and timing violations.

Qualifications

• Master’s degree in Electrical Engineering or related field; 5 years of related experience.
• Experience with EDA tools: Innovus, IC Compiler, Primetime or Calibre.
• Experience in synthesis, place & route, and PD verification flows.
• Understanding timing convergence and low power verification.
• Clock gating/power gating and multi-voltage design techniques.
• HDL languages to describe digital circuits.
• Automation using scripting: Perl, Shell, Makefiles, TCL.
• Block/IP floorplanning and macro placement; routing/congestion analysis.

Responsibilities

• Perform physical design implementation of SOC blocks from netlist to tape-out.
• Collaborate with RTL/design teams to understand data flow and place memories/macros.
• Improve methodologies, create guidelines and checklists, track progress.
• Analyze reports and write scripts to develop solutions; fix violations.
• Perform STA, IR drop, LVS/DRC checks and clean up violations.
• Interact with integration, timing, and electrical analysis teams.

Education

Master's degree in Electrical Engineering

Tools

Innovus

IC Compiler

Primetime

Calibre

Job description

Apple Inc. in Austin, Texas is seeking a seasoned physical design engineer to implement System-On-Chip blocks from netlist through tape-out in advanced nodes.

You will collaborate with RTL teams to optimize placement, clock distribution and power integrity, drive design methodologies, and analyze STA/DRC/LVS reports. The role emphasizes automation, scripting, and continuous improvement of block construction recipes to reduce area, power, and timing violations.