Senior SoC Physical Design Lead: High-Perf & Low-Power

Apple Inc.; Austin (TX); On-site; USD 180,000 - 280,000; Full time

Job summary

Apple Inc. in Austin, TX seeks a seasoned Physical Design technical leader with deep expertise in high-performance and low-power design to guide PD architecture from RTL to GDS and ensure timing, area, and power targets are met.

You will own end-to-end PD implementation, drive methodologies, and serve as the primary technical contact for your focus area, collaborating with cross-functional teams to resolve timing closures and enable successful tapeouts.

Qualifications

• BS and 3+ years of relevant industry experience.
• Knowledge of PD construction & analysis flows and methodology.
• Strong interpersonal skills and collaboration abilities.
• Experience with submicron processes and large SOCs.

Responsibilities

• Own physical design implementation from RTL to GDSII, including PnR, bump/RDL, STA, physical verification, EMIR, and sign-off.
• Collaborate to drive methodologies and best-known methods to streamline PD work and develop guidelines and checklists.
• Serve as the primary technical contact for your focus area and address timing, area, and power optimization challenges.

Skills

Interpersonal skills

Timing closure

Power optimization

Die size management

Team collaboration

Education

Bachelor's degree

Tools

Industry standard PD tools

Job description

Apple Inc. in Austin, TX seeks a seasoned Physical Design technical leader with deep expertise in high-performance and low-power design to guide PD architecture from RTL to GDS and ensure timing, area, and power targets are met.

You will own end-to-end PD implementation, drive methodologies, and serve as the primary technical contact for your focus area, collaborating with cross-functional teams to resolve timing closures and enable successful tapeouts.