Physical Design Engineer

Proxelera PVT LTD; Mountain View (CA); On-site; USD 140,000 - 210,000; Full time

Job summary

Proxelera PVT LTD seeks a Physical Design Engineer to drive block-level implementation from netlist to GDSII in a high-performance environment.

You will perform floorplanning, power planning, CTS, routing, and timing convergence, ensuring robust PPA and signoffs across advanced nodes.

Qualifications

• Candidate has solid experience in physical design and PnR flow for advanced nodes.
• Demonstrated ability to drive floorplanning, CTS, routing and timing convergence.
• Experience with EMIR analysis and signoff methodologies.

Responsibilities

• Drive block-level physical design from netlist to GDSII.
• Perform floorplanning, power planning, placement, CTS, routing and verification.
• Optimize designs for Power, Performance and Area targets.
• Achieve timing closure across corners and modes.
• Analyze and resolve setup/hold/transition violations and noise.
• Develop and maintain timing constraints (SDC) and STA signoff.
• Perform EMIR analysis and closure.
• Collaborate with RTL/DFT/STA teams for tapeout.

Skills

Physical Design

PnR Flow

Floorplanning

Placement & Optimization

Clock Tree Synthesis

Routing

Timing Closure

STA

SDC

EMIR Analysis

PPA Optimization

Low-Power Techniques

Cross-Functional Collaboration

Education

Bachelor's or Master's degree in Electrical/Electronics Engineering

Tools

Cadence Innovus

RedHawk

Voltus

Job description

We are looking for a Physical Design Engineer with strong expertise in Place & Route (PnR), Power-Performance-Area (PPA) optimization, and timing convergence for advanced technology nodes.

Key Responsibilities

• Drive block-level physical design implementation from netlist to GDSII.
• Perform floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical verification.
• Optimize designs for Power, Performance, and Area (PPA) targets.
• Achieve timing closure across multiple corners and modes.
• Analyze and resolve setup, hold, transition, capacitance, and noise violations.
• Develop and maintain timing constraints (SDC) and STA signoff methodologies.
• Perform EMIR (Electromigration & IR Drop) analysis and closure.
• Collaborate with RTL, DFT, STA, and Signoff teams to ensure successful tapeout.
• Debug physical design issues and drive design convergence within project schedules.

Required Skills

• Strong experience in Physical Design and PnR flow.
  • Floorplanning
  • Placement & Optimization
  • Clock Tree Synthesis (CTS)
  • Routing
  • Timing Closure
  • Static Timing Analysis (STA)
  • Timing Constraints (SDC)
  • EMIR Analysis
  • PPA Optimization
• Experience with industry-standard EDA tools such as:
  • Cadence Innovus (optional)
  • RedHawk / Voltus (EMIR)
• Good understanding of low-power design techniques and signoff methodologies.

Preferred Qualifications

• Bachelor's or Master's degree in Electrical/Electronics Engineering.
• Experience in advanced nodes (7nm/5nm/3nm preferred).
• Strong debugging and problem-solving skills.
• Experience working with cross-functional silicon teams.