Global Director, Ultra-Low Power ASIC Physical Design

NOKIA; San Jose (CA); On-site; USD 250,000 - 420,000; Full time

Job summary

Nokia seeks an experienced Director of ASIC Physical Design to strategically lead global physical design engineering teams. Drive end-to-end PD from RTL to GDSII with emphasis on ultra-low power and PPA on latest nodes.

Define advanced methodologies and manage multi-site teams across USA, India, and Italy to ensure first-pass silicon success. The candidate will mentor teams, implement Customer Owned Tooling flows, optimize flows for new processes, and collaborate with architecture, RTL, CAD, and

Qualifications

• Master's degree required in EE/CE or related field.
• 15+ years in ASIC physical design with 8+ years in leadership.
• Expertise in floorplanning, power, placement, CTS, routing, timing, DRC/LVS.
• Proven track record of multiple ASIC tape-outs on advanced nodes (7nm/5nm/3nm).
• Experience with CoT flow and GDSII release.
• Knowledge of AI for PD flow and automation.
• Strong leadership and global collaboration skills.
• Experience with memory compilers, SerDes, hard IP integration.

Responsibilities

• Define and execute the physical design roadmap; lead distributed teams across the USA, India, and Italy.
• Mentor and grow a high-performing global team; drive advanced methodologies and CoT tooling adoption for robust GDSII release.
• Develop and continuously improve PD methodologies and flows for leading-edge nodes with emphasis on low power techniques.
• Oversee full physical design cycle: floorplan, power grid, placement, CTS, routing, STA, IR/EM, DRC/LVS, DFY; optimize for aggressive PPA targets.
• Collaborate with architecture, RTL, DFT, CAD, packaging and test teams to ensure successful first-pass silicon under tight schedules.
• Manage vendor & IP relationships with EDA tool vendors and IP providers; evaluate new tech and tool deployment.
• Identify technical risks and develop mitigation strategies; manage budget and resources across global sites.
• Ensure efficient execution and delivery through cross-site coordination and devops for PD.

Skills

Strategic leadership

Global team mgmt

ASIC PD

PPA optimization

Low-power design

Flow methodology

Cross-functional collab

Risk management

Budget planning

Hiring top talent

Education

Master's degree in EE/CE or related field

Ph.D. preferred

Tools

Synopsys

Cadence

Siemens EDA

Job description

Nokia seeks an experienced Director of ASIC Physical Design to strategically lead global physical design engineering teams. Drive end-to-end PD from RTL to GDSII with emphasis on ultra-low power and PPA on latest nodes.

Define advanced methodologies and manage multi-site teams across USA, India, and Italy to ensure first-pass silicon success. The candidate will mentor teams, implement Customer Owned Tooling flows, optimize flows for new processes, and collaborate with architecture, RTL, CAD, and