Data Center Power & Limits Architect for SoCs

Qualcomm; Austin (TX); On-site; USD 164,000 - 246,000; Full time

Job summary

Qualcomm Technologies, Inc. seeks a Data Center Power & Limits Architect to define end-to-end power, thermal, and limits systems for large-scale compute platforms.

You will drive architectural decisions across silicon, platform, and data-center infrastructure to maximize sustained performance under constrained power and cooling envelopes, balancing efficiency and reliability in AI/HPC workloads. Collaborate with Silicon/SoC, Platform, Software, and Data Center teams to implement DVFS, telemetry

Qualifications

• 10+ years of experience in power architecture or related domains.
• Expertise in power management, thermal limits, and DVFS/DCVS.
• Understanding of data center/server architecture and telemetry.
• Experience with modeling tools like MATLAB or Python.

Responsibilities

• Define holistic power, thermal, and electrical limits architecture across silicon to data center.
• Architect power budgeting and enforcement across CPU, GPU, memory, accelerators, and I/O.
• Develop strategies to maximize performance under datacenter constraints.
• Design dynamic power control systems and closed-loop telemetry.
• Enable real-time monitoring and integration with platform controllers.
• Collaborate across silicon, platform, software, and data center teams.

Skills

Power architecture

Thermal constraints

DVFS/DCVS

Power capping

Telemetry & monitoring

Data center/server architecture

Education

Bachelor's degree in Science, Engineering, or related field

Master's degree in Science, Engineering, or related field

PhD in Science, Engineering, or related field

Tools

MATLAB

Simulink

Python

Job description

Qualcomm Technologies, Inc. seeks a Data Center Power & Limits Architect to define end-to-end power, thermal, and limits systems for large-scale compute platforms.

You will drive architectural decisions across silicon, platform, and data-center infrastructure to maximize sustained performance under constrained power and cooling envelopes, balancing efficiency and reliability in AI/HPC workloads. Collaborate with Silicon/SoC, Platform, Software, and Data Center teams to implement DVFS, telemetry