GPU Front-End Implementation Engineer

Apple Inc.; Santa Clara, Northern (CA, KY); Hybrid; USD 185,000 - 325,000; Full time

Job summary

Apple Inc. is seeking a seasoned RTL/IP engineer in Santa Clara, CA to drive block-level synthesis and optimization for Apple Silicon GPUs.

You will work with RTL and physical design teams to meet tight timing and power targets, while applying advanced RTL/Synthesis/PNR techniques and collaborating with STA/DFT partners to deliver best-in-class silicon. The role emphasizes cross-domain problem solving, multi-clock and multi-power domain handling, and the development of innovative methodologies

Qualifications

• Experience driving block level synthesis and optimizations.
• Experience with RTL design improvement for optimal Area, Timing Power.
• Experience debugging complex logic equivalence issues and in netlist checks to validate functionality and netlist quality.
• Experience implementing ECOs for functionality and timing.
• Experience with reset domain, multi-clock domain, multi-power domain (UPF), linting tools across RTL and Gate-Level.
• Scripting experience in ASIC flows – python, tcl, Perl, Data manipulation.
• BS + 10 years of relevant experience.

Responsibilities

• Synthesize, analyze, and optimize delivered IP to meet timing, power, and area targets.
• Collaborate with RTL, PD, STA and DFT teams to achieve successful first silicon.
• Develop and apply advanced RTL/Synthesis/PNR techniques for GPU IP under Apple Silicon.

Skills

Block level synthesis

RTL optimization

Debugging netlist issues

ECOs for timing

UPF/multi-clock domain

Scripting (Python/TCL/Perl)

BS + 10 years experience

Job description

Apple Inc. is seeking a seasoned RTL/IP engineer in Santa Clara, CA to drive block-level synthesis and optimization for Apple Silicon GPUs.

You will work with RTL and physical design teams to meet tight timing and power targets, while applying advanced RTL/Synthesis/PNR techniques and collaborating with STA/DFT partners to deliver best-in-class silicon. The role emphasizes cross-domain problem solving, multi-clock and multi-power domain handling, and the development of innovative methodologies