Senior CPU Gate-Level Synthesis Engineer

Apple Inc.; Santa Clara (CA); On-site; USD 184,700 - 324,800; Full time

Job summary

Apple's Silicon Engineering Group (SEG) is seeking a CPU Gate Level Synthesis Engineer to drive early-stage development of high-performance, low-power CPUs. You will run RTL to gate-level synthesis and seek opportunities to optimize timing, power, and area while collaborating across RTL, physical design and DFT teams.

The role requires a BS and 10+ years in digital logic, RTL synthesis and physical design, with preferred CPU implementation experience and scripting skills in Tcl, Perl or Python.

Qualifications

• BS degree with 10+ years of relevant industry experience.
• Experience in digital logic design, RTL synthesis, and physical design.
• CPU implementation experience is a plus.

Responsibilities

• Early RTL health assessment to detect potential timing/gate-depth issues and collaborate with RTL and physical design teams.
• Early stage power estimation and validation for new micro-architectural features.
• Enhance synthesis flows for good correlation to post-route to ensure high fidelity of synthesis-based feedback.
• Work closely with DFT teams to ensure seamless integration of scan chain, ATPG, and MBIST into the synthesis flow.
• Partner with timing team to enable constraints generation at top levels.
• Debug and resolve timing, power, and area issues, ensuring efficient and scalable designs.
• Track and analyze PPA trends through project cycle.

Skills

Digital logic design

RTL synthesis

Physical design

CPU implementation experience

Tcl scripting

Perl scripting

Python scripting

Cross-functional collaboration

Education

Bachelor's degree

Tools

Tcl

Perl

Python

Job description

Apple's Silicon Engineering Group (SEG) is seeking a CPU Gate Level Synthesis Engineer to drive early-stage development of high-performance, low-power CPUs. You will run RTL to gate-level synthesis and seek opportunities to optimize timing, power, and area while collaborating across RTL, physical design and DFT teams.

The role requires a BS and 10+ years in digital logic, RTL synthesis and physical design, with preferred CPU implementation experience and scripting skills in Tcl, Perl or Python.