SoC DFT Engineer for AI/TPU Cloud | Equity

Google LLC; Sunnyvale (CA); On-site; USD 163,000 - 236,000; Full time

Benefits offered by this job

Equity compensation

Bonus target

Job summary

Google LLC in Sunnyvale, CA is seeking a DFT Engineer to shape the future of AI/ML hardware acceleration. You will drive TPU architecture and verify complex digital designs with emphasis on DFT methodologies across IP blocks, including scan, MBIST, JTAG, and iJTAG.

You will define silicon test strategies, DFT/DFD architecture, and create debug specifications for next-gen SoCs, partnering with Silicon Engineering to diagnose memory/logic failures and improve yield while reducing test cost.

Qualifications

• Bachelor's degree in EE/CE/CS or related field required.
• 5 years of experience in DFT architecture, implementation, and verification for SoCs.
• Experience in silicon bring-up, debug, or validation of DFT features.
• Experience with industry-standard test methodologies and platforms such as ATE, MBIST, JTAG, or System Level Test (SLT).

Responsibilities

• Develop and document DFT strategy, architecture and test sequences, including hierarchical DFT, MBIST, ATPG and I/JTAG, and associated boot up and execution sequences.
• Complete all Test Design Rule Checks (TDRC) and Design changes to fix TDRC violations to achieve high test quality.
• Develop diagnostic databases, software and hardware for logic and memory fail debug.
• Design and implement system level test strategy.
• Implement core DFT circuitry, including insertion and hook-up of scan chains, DFT compression, Logic BIST, TAP controllers, and MBIST logic for IP blocks.

Skills

DFT architecture experience

Silicon bring-up/debug/validation

ATE/MBIST/JTAG/SLT

10+ years DFT experience

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Master's or PhD in Electrical Engineering, Computer Engineering or Computer Science

Tools

Synopsys DFT tools

Siemens EDA Tessent

Job description

Google LLC in Sunnyvale, CA is seeking a DFT Engineer to shape the future of AI/ML hardware acceleration. You will drive TPU architecture and verify complex digital designs with emphasis on DFT methodologies across IP blocks, including scan, MBIST, JTAG, and iJTAG.

You will define silicon test strategies, DFT/DFD architecture, and create debug specifications for next-gen SoCs, partnering with Silicon Engineering to diagnose memory/logic failures and improve yield while reducing test cost.