SoC Test Engineer (DFT)

Mogi I/O : OTT/Podcast/Short Video Apps for you; Austin (TX); On-site; USD 170,000 - 200,000; Full time

Job summary

A well-funded hardware startup in Austin is seeking an experienced DFT Engineer to innovate and own design-for-test methodologies for advanced digital and mixed-signal SoCs. Candidates should have 5-8 years of relevant experience and a master's degree in Electrical Engineering. This full-time role focuses on cross-functional collaboration to deploy robust DFT strategies for next-generation programmable DSP chips, targeting the fastest AI and cloud infrastructures.

Qualifications

• 5+ years in DFT spec, architecture, insertion, and analysis for complex silicon.
• Experience in silicon bring-up, debug/validation of DFT on ATE, ATPG, MBIST, JTAG.
• ASIC DFT, synthesis, simulation/verification know-how.
• Strong organizational/problem-solving skills; detail oriented.
• Willing to work on-site in Austin, TX (Relocation not covered).

Responsibilities

• Lead and implement SoC DFT architecture and ATPG/MBIST strategy.
• Insert, validate, and debug all DFT logic – scan chains, BIST, boundary scan, TAP, compression, MBIST.
• Own silicon bring-up and ATE debug for new test features and DFT IP.
• Collaborate to improve test coverage, resolve RTL violations, and streamline test processes.
• Develop and maintain formal DFT documentation.

Skills

DFT Specification & Architecture

ATPG, MBIST, JTAG

Silicon Bring-up & Test (ATE)

Scan Chains, DFT Compression, Logic BIST

EDA Test Tools

IP Integration, ASIC Synthesis & Verification

Problem-Solving

Communication

Education

Master’s degree in Electrical Engineering

Tools

DFT Max

Tessent

Modus

Design/Fusion Compiler

SpyGlass

TestKompress

Job description

Location: Austin, Texas (Onsite, 5 days/week)
Industry: Semiconductor, AI Infrastructure, Cloud Hardware
Salary: $170,000–$200,000 USD + Equity (4-year vesting)
Experience: 5–8 years (DFT specialization required)
Visa: H1-B sponsorship available

Summary: Well-funded hardware startup (with $180MM in recent funding, backed by leading VCs) seeks an experienced DFT Engineer to innovate and own design-for-test (DFT) methodologies for advanced digital and mixed-signal SoCs. This hands-on role collaborates cross-functionally to define, implement, and deploy robust DFT strategies for next-generation programmable DSP chips powering the world’s fastest AI and cloud infrastructure.

Skills:

• DFT Specification & Architecture
• ATPG, MBIST, JTAG
• Silicon Bring-up & Test (ATE)
• Scan Chains, DFT Compression, Logic BIST
• EDA Test Tools (DFT Max, Tessent, Modus, SpyGlass, Design/Fusion Compiler, TestKompress)
• IP Integration, ASIC Synthesis & Verification
• Problem-Solving, Communication

• 5+ years in DFT spec, architecture, insertion, and analysis for complex silicon
• Experience in silicon bring-up, debug/validation of DFT on ATE, ATPG, MBIST, JTAG
• ASIC DFT, synthesis, simulation/verification know-how
• Strong organizational/problem-solving skills; detail oriented
• Willing to work on-site in Austin, TX (Relocation not covered)

• Master’s degree in Electrical Engineering
• IP integration (memories, test controllers, MBIST, TAP)
• Expert use of EDA tools: DFT Max, Tessent, Modus, Design/Fusion Compiler, SpyGlass, TestKompress
• Silicon test coverage improvement, hierarchical design/test

• Lead and implement SoC DFT architecture and ATPG/MBIST strategy
• Insert, validate, and debug all DFT logic – scan chains, BIST, boundary scan, TAP, compression, MBIST
• Own silicon bring-up and ATE debug for new test features and DFT IP
• Collaborate to improve test coverage, resolve RTL violations, and streamline test processes
• Develop and maintain formal DFT documentation

Seniority level: Mid-Senior level

Employment type: Full-time

Job function: Engineering and Information Technology

Industries: Software Development