ASIC/SoC Silicon Test Engineer

Anysilicon; Sunnyvale (CA); Hybrid; USD 130,000 - 190,000; Full time

Job summary

Google is seeking a Test Engineer to join the AI and Infrastructure team in Sunnyvale to shape the future of AI/ML hardware acceleration for TPUs. You will develop and implement silicon test requirements with internal design teams and external vendors, and drive post-silicon testing best practices.

You will collaborate with cross-functional teams on NPIs, bring-up, verification, characterization, and qualification, optimizing test coverage and yielding improvements from test data analytics.

Qualifications

• Bachelor's degree in CS, EE, or related field.
• 5 years of test engineering or product engineering experience.
• Experience in ASIC or SoC test development, bring-up, or debug.

Responsibilities

• Develop and implement silicon test requirements with design teams and vendors.
• Execute strategies for SoC product NPI, bring-up, verification, characterization, and qualification support.
• Optimize test coverage and troubleshoot issues during testing.
• Drive quality improvements using ATE test experience and expertise.
• Collaborate with design, DFT, and quality teams to establish post-silicon testing best practices.
• Support chip production with test program upgrades, volume data analytics, and yield improvement.

Skills

Test engineering

SoC test experience

Quality assurance

Education

Bachelor's degree in Computer Science or Electrical Engineering

Tools

ATPG test development

ATE (Advantest, Teradyne)

PCIe/Memory test techniques

Job description

Join Google’s AI and Infrastructure team as a Test Engineer, where you will play a pivotal role in shaping the future of AI/ML hardware acceleration. This position focuses on developing and implementing test solutions for Tensor Processing Units (TPUs) that power Google's most demanding applications. You will collaborate with cross-functional teams to ensure high-quality SoCs and contribute to innovations that impact millions of users worldwide.

Responsibilities:

• Develop and implement silicon test requirements with internal design teams and external vendors.
• Execute strategies for SoC product NPI, bring-up, verification, characterization, and qualification support.
• Optimize test coverage and troubleshoot issues during the testing phase.
• Drive quality improvements using ATE test experience and expertise.
• Collaborate with design, DFT, and quality teams to establish best practices for post-silicon testing.
• Support chip production with test program upgrades, volume data analytics, and yield improvement.

Qualifications:

• Bachelor's degree in Computer Science, Electrical Engineering, or a related field, or equivalent practical experience.
• 5 years of experience in test engineering or product engineering.
• Experience in ASIC or SoC test development, bring-up, or debug.

Skills:

• Master's degree in a related technical field is preferred.
• 10 years of experience in test engineering, product engineering, or silicon quality/reliability.
• Experience with scan/ATPG test development or memory BIST test development.
• Familiarity with testing IPs such as PLLs, PVT sensors, and eFuse.
• Experience with Automatic Test Equipment (ATE) from Advantest and Teradyne.

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

Find the Right Semiconductor Partner

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP