Senior SoC DFT Engineer for AI/ML TPU Architectures

Google; Sunnyvale (CA); On-site; USD 163,000 - 236,000; Full time

Job summary

Google is seeking a DFT Engineer to shape AI/ML hardware acceleration via TPU integration. You will verify complex digital designs with a focus on TPU architecture within AI/ML systems and drive advanced test methodologies across silicon IP blocks.

You will define silicon test strategies, DFT/DFD architectures, and collaborate with Silicon Engineering to diagnose memory and logic failures, improving yield and reducing test cost.

Qualifications

• Bachelor’s degree or equivalent practical experience in EE/CS.
• 5 years of experience in DFT architecture, implementation, and verification for SoCs.
• Experience with silicon bring-up, debug, or validation of DFT features.
• Experience with ATE, MBIST, JTAG, or SLT test methodologies and platforms.

Responsibilities

• Develop and document DFT strategy, architecture and test sequences (MBIST, ATPG, I/JTAG).
• Complete all TDRC checks and related design changes to ensure high test quality.
• Develop diagnostic databases, software and hardware for logic and memory fail debug.
• Design and implement system level test strategy for IP blocks and chips.
• Implement DFT circuitry including scan chains, DFT compression, LBST, TAP controllers, MBIST logic.

Skills

DFT architecture

DFT verification

silicon bring-up

test methodologies

Education

Bachelor’s degree or equivalent practical experience

Master’s or PhD in Electrical/Computer Engineering or CS

Tools

Synopsys Design Compiler

Synopsys DFT Max

Siemens Tessent

Siemens TestKompress

Job description

Google is seeking a DFT Engineer to shape AI/ML hardware acceleration via TPU integration. You will verify complex digital designs with a focus on TPU architecture within AI/ML systems and drive advanced test methodologies across silicon IP blocks.

You will define silicon test strategies, DFT/DFD architectures, and collaborate with Silicon Engineering to diagnose memory and logic failures, improving yield and reducing test cost.