SoC DFT Engineer, Cloud

Google; United States; On-site; USD 163,000 - 236,000; Full time

Job summary

Google is seeking a mid-level SoC DFT Engineer specializing in design-for-test methodologies to shape the future of AI/ML hardware acceleration. You’ll verify complex digital designs, focusing on TPU architecture integration within AI/ML systems and collaborating with silicon engineering to improve yield and reduce test cost.

You will implement Scan, MBIST, JTAG, and iJTAG for IP blocks, define silicon test strategies, and contribute to next-generation TPU-related SoCs and test flows.

Qualifications

• Bachelor's degree or equivalent practical experience.
• 5 years of experience in DFT architecture, implementation, and verification for SoCs.
• Experience in silicon bring-up, debug, or validation of DFT features.
• Experience with industry-standard test methodologies and platforms, such as ATE, MBIST, JTAG, or System Level Test (SLT).

Responsibilities

• Develop and document DFT strategy, architecture, and test sequences, including hierarchical DFT, MBIST, ATPG, and I/JTAG.
• Complete all Test Design Rule Checks (TDRC) and fix Design changes to achieve high test quality.
• Develop diagnostic databases, software, and hardware for logic and memory fail debug.
• Design and implement system-level test strategy.
• Implement core DFT circuitry, including scan chains, DFT compression, Logic BIST, TAP controllers, and MBIST logic for IP blocks.

Skills

DFT verification

System-level test

Test methodology

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science (preferred)

Tools

ATE

MBIST

JTAG

SLT

Job description

SoC DFT Engineer, Cloud

Location: Sunnyvale, CA, USA

Experience Level: Mid

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 5 years of experience in DFT architecture, implementation, and verification for SoCs.
• Experience in silicon bring-up, debug, or validation of DFT features.
• Experience with industry-standard test methodologies and platforms, such as ATE, MBIST, JTAG, or System Level Test (SLT).

Preferred Qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science, with an emphasis on computer architecture.
• 10 years of experience in DFT architecture, implementation, and verification for SoCs.
• Experience with various fault models (e.g., Stuck-at, Transition, Cell-Aware, Path Delay, etc.).
• Experience in DFT flow, including architecture, IP integration (e.g., Test controllers, TAP, MBIST), and interaction with synthesis and verification flows.
• Experience with industry-leading EDA tools for DFT, such as Synopsys (e.g., Design Compiler, DFT Max) or Siemens EDA (e.g., Tessent, TestKompress).
• Knowledge of test standards (e.g., IEEE 1149.1, 1687) and test data Formats (e.g., BSDL, STIL).

About the Job

In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As a DFT Engineer, you will be responsible for defining, implementing, and deploying advanced design-for-test (DFT) methodologies including Scan, MBIST, JTAG, and iJTAG, for highly digital or mixed-signal chips or IPs. You will define silicon test strategies, DFT/DFD architecture, and create DFT and Debug specifications for next-generation SoCs. In partnership with the Silicon Engineering team, you will also be responsible for diagnosing memory and logic failures, increasing production quality, and enhancing yield while reducing test cost.

The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability, and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware, our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US Salary: $163,000 - $236,000 (USD) + 15% bonus target + equity + benefits

Responsibilities

• Develop and document DFT strategy, architecture, and test sequences, including hierarchical DFT, MBIST, ATPG, and I/JTAG, and associated boot-up and execution sequences.
• Complete all Test Design Rule Checks (TDRC) and Design changes to fix TDRC violations to achieve high test quality.
• Develop diagnostic databases, software, and hardware for logic and memory fail debug.
• Design and implement system-level test strategy.
• Implement core DFT circuitry, including insertion and hook-up of scan chains, DFT compression, Logic BIST, TAP controllers, and Memory BIST (MBIST) logic for IP blocks.

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Equal Opportunity

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Google is a global company, and in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

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