SoC DFT Engineer for AI/ML Accelerated Chips — Equity

Google Inc.; Sunnyvale (CA); On-site; USD 163,000 - 237,000; Full time

Benefits offered by this job

15% bonus target

Equity options

Comprehensive benefits package

Job summary

Google Inc. is seeking an experienced DFT Engineer to shape the future of AI/ML hardware acceleration in Sunnyvale, California. You will drive TPU technology that powers Google's AI/ML applications, managing the design and verification of complex digital circuits.

Applicants should have extensive experience in DFT architecture and a strong educational background in Electrical Engineering or related fields. A competitive salary range of $163,000 - $237,000, plus bonuses and equity, is offered.

Qualifications

• 5+ years of experience in DFT architecture and verification for SoCs.
• Experience with ATE, MBIST, JTAG, or SLT methodologies.
• Mastery of various fault models like Stuck-at, Transition, and Path Delay.

Responsibilities

• Define, implement, and deploy advanced DFT methodologies.
• Design silicon test strategies and DFT architecture for SoCs.
• Diagnose memory and logic failures to enhance production quality.

Skills

DFT architecture expertise

Debug and validation experience

Knowledge of test methodologies

Silicon bring-up experience

Education

Bachelor's degree in Electrical Engineering or related

Master's degree or PhD in relevant field

Tools

Synopsys EDA tools

Siemens EDA tools

Job description

Google Inc. is seeking an experienced DFT Engineer to shape the future of AI/ML hardware acceleration in Sunnyvale, California. You will drive TPU technology that powers Google's AI/ML applications, managing the design and verification of complex digital circuits.

Applicants should have extensive experience in DFT architecture and a strong educational background in Electrical Engineering or related fields. A competitive salary range of $163,000 - $237,000, plus bonuses and equity, is offered.