SoC Design Engineer II – IO/Peripheral Integration (Remote/On-site)

Apex Systems; Burlingame (CA); On-site; USD 156,000 - 169,000; Full time

Benefits offered by this job

ESPP (Employee Stock Purchase Plan)

401(k) program with company match

HSA health savings account

EAP with free counseling sessions

Career development & training programs

Job summary

Everforth Apex is seeking a Digital Design Engineer II in Burlingame, CA to join our core engineering team. You will integrate low-speed peripheral IPs (I3C/I2C/SPI/UART) into the SoC, manage IO cells, and develop glue logic and test tooling for RTL-to-GDS workflows.

The role requires 4+ years of hands-on experience with IO mux architecture, UPF low-power flows, and SystemVerilog verification, with a focus on robust subsystem integration.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering, Computer Science, or equivalent experience.
• 4+ years as a Digital Design Engineer with SoC/subsystem integration experience.
• Hands-on integration with I3C, I2C, SPI/QSPI/OSPI and UART controllers.

Responsibilities

• Integrate I3C, I2C, SPI/QSPI/OSPI and UART controller IPs into the peripheral subsystem and SoC top.
• Own IO-level integration including pad/IO cell selection and IO mux design.
• Develop glue logic such as bus bridging, register maps, clock/reset generation, and interrupt/DMA routing.
• Support RTL-to-GDS, constraints, synthesis, timing closure and low-power UPF intent.
• Extend Python-based integration tools for IO mux tables and pinmux collateral.
• Support FPGA prototyping, bring-up, validation and test program development.

Skills

Verilog RTL

SystemVerilog

Python scripting

Tcl scripting

UPF flows

UVM/OVM

IO mux

Education

Bachelor's in Electrical/Computer Engineering

Tools

CAN/CAN-FD

Job description

Everforth Apex is seeking a Digital Design Engineer II in Burlingame, CA to join our core engineering team. You will integrate low-speed peripheral IPs (I3C/I2C/SPI/UART) into the SoC, manage IO cells, and develop glue logic and test tooling for RTL-to-GDS workflows.

The role requires 4+ years of hands-on experience with IO mux architecture, UPF low-power flows, and SystemVerilog verification, with a focus on robust subsystem integration.