Design Engineer II # 26-23167

US Tech Solutions; Burlingame (CA); Hybrid; USD 140,000 - 312,000; Full time

Benefits offered by this job

Hybrid/Remote work

Job summary

US Tech Solutions in Burlingame, CA seeks a Contract Digital Design Engineer to integrate low-speed peripheral subsystems (I3C/I2C, SPI/QSPI/OSPI, UART) into an SoC. You will own IO-level integration, IO mux design, and programability, including pad state during reset and power modes.

You will develop glue logic, bus bridges, clock/reset generation, and contribute to μArchitecture and RTL verification. This 8-month contract requires strong Verilog/SystemVerilog, Python scripting, and

Qualifications

• 4+ years as a Digital Design Engineer with SoC/subsystem integration ownership.
• Hands-on integration of I3C, I2C, SPI/QSPI/OSPI and UART controllers.
• Strong Verilog/SystemVerilog RTL coding and μArchitecture definition.
• Python scripting for integration tooling and familiarity with Tcl-based flows.
• UPF-based low-power flows and SystemVerilog UVM/OVM exposure.
• BS in Electrical/Computer Engineering or equivalent.

Responsibilities

• Integrate I3C, I2C, SPI/QSPI/OSPI and UART controller IPs into the peripheral subsystem and SoC top.
• Own IO-level integration: pad/IO cell selection, IO mux design, programmability and pull-ups.
• Develop glue logic: bus bridging, register maps, clock/reset generation, CDC and DMA routing.
• Contribute to μArchitecture, RTL verification plans, and verification support.
• Extend Python-based tooling for IO mux tables, pinmux collateral and connectivity.

Skills

Digital design

Verilog/SystemVerilog

Python scripting

IO/pads knowledge

SoC integration

UVM/OVM exposure

Education

Bachelor's degree

Tools

Python

Tcl

Synthesis tools

Job description

$70-$150 per hour

Burlingame, CA

Contract

Duration: 8 Months Contract

Summary:

• Overview Contract digital design engineer to integrate the low-speed peripheral subsystem I3C, I2C, SPI/QSPI/OSPI, UART controllers — including the IO cells, pad ring connectivity and IO multiplexing that these peripherals depend on.

• Duties Integrate I3C, I2C, SPI/QSPI/OSPI and UART controller IPs into the peripheral subsystem and SoC top Own IO-level integration: pad/IO cell selection and configuration, IO mux design and programmability, pull-up/pull-down, drive strength, open-drain vs. push-pull, bidirectional/tri-state control, retention and pad state during reset/power modes.

• Develop glue and control logic: bus bridging (APB/AHB/AXI), register maps, clock and reset generation/gating, interrupt and DMA request routing, CDC Contribute to subsystem μArchitecture and top-level RTL; drive integration, verification plan development and verification support; apply Design-for-Verification concepts Extend and maintain our Python-based integration/generation tooling (IO mux tables, pinmux collateral, connectivity and register generation)

• Support RTL-to-GDS: constraints, synthesis, timing closure, low-power (UPF) intent for the peripheral/IO domain Support FPGA prototyping, bring-up/validation, test program development and chip life to production maturity

Must Have

• 4+ years as a Digital Design Engineer, with SoC/subsystem integration ownership Hands-on integration of I3C, I2C, SPI/QSPI/OSPI and UART controllers

• Practical understanding of IOs/pads used for peripherals and of IO mux architecture and pinmux collateral

• Strong Verilog/SystemVerilog RTL coding; digital μArchitecture definition

• Python scripting — required, our integration tools are Python-based Tcl scripting; familiarity with synthesis and static timing

• Experience with UPF-based simulation/low-power flows SystemVerilog UVM/OVM exposure

• BS in Electrical/Computer Engineering or Computer Science, or equivalent experience

• Familiarity with AI assisted code

• IO system operations experience

Nice to Have

CAN / CAN-FD protocol and CAN controller integration experience I3C advanced features (in-band interrupts, hot-join, dynamic address assignment, HDR modes) Sensor-hub or MCU subsystem integration; boot-from-flash (QSPI/OSPI, XIP) experience DFT/testability and test-program definition; Power-Aware GLS FPGA prototyping; PCIe/USB/MIPI exposure MSEE/CS Synopsys Core Consultant experience (IP configuration/generation and coreAssembler-based subsystem assembly)

Education:

• Bachelors in Engineering required.

Note:

• US - CA - Burlingame (Hybrid/Remote)

About US Tech Solutions:

US Tech Solutions is a global staff augmentation firm providing a wide range of talent on-demand and total workforce solutions. To know more about US Tech Solutions, please visit www.ustechsolutions.com .

US Tech Solutions is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, colour, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.

AI Statement:

By applying, you acknowledge that AI-assisted tools may be used during hiring.

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