Logic Design Engineer, Mixed-Signal & High-Speed IO

AMD; Santa Clara (CA); On-site; USD 150,000 - 190,000; Full time

Benefits offered by this job

AMD benefits

Job summary

AMD in Santa Clara, CA is seeking an adaptive design engineer for the mixed-signal high-speed IO team. You will develop Verilog RTL, create microarchitecture specs, and drive ASIC flows while collaborating with verification and physical design to ensure timing and silicon quality.

The role requires strong analytical skills, initiative to drive tasks, and the ability to mentor junior engineers in a fast-paced environment. Visa sponsorship is not offered for this position.

Qualifications

• Experience in analog mixed-signal design from specification to silicon.
• Experience with high-speed interfaces (DDR, GDDR, HBM, SERDES).
• Experience with multiple power and clock domains.

Responsibilities

• Analyze complex digital design problems and propose architectures.
• Develop Verilog RTL and Functional Behavioral Models.
• Drive ASIC design flows and scripts.
• Create microarchitecture specifications.
• Collaborate with Design Verification for functional correctness.
• Collaborate with Physical Design for timing closure.
• Deliver improvements, optimizations, and power-saving enhancements.
• Support silicon bring-up and diagnostics.

Skills

Analog mixed-signal design

High-speed interfaces

leadership/mentoring

Education

BS in electrical engineering

MS in electrical engineering

Tools

ASIC CAD tools

Job description

AMD in Santa Clara, CA is seeking an adaptive design engineer for the mixed-signal high-speed IO team. You will develop Verilog RTL, create microarchitecture specs, and drive ASIC flows while collaborating with verification and physical design to ensure timing and silicon quality.

The role requires strong analytical skills, initiative to drive tasks, and the ability to mentor junior engineers in a fast-paced environment. Visa sponsorship is not offered for this position.