Core Engineering - Design Engineer II

Apex Systems; Burlingame (CA); On-site; USD 156,000 - 169,000; Full time

Benefits offered by this job

ESPP (Employee Stock Purchase Plan)

401(k) program with company match

HSA health savings account

EAP with free counseling sessions

Career development & training programs

Job summary

Everforth Apex is seeking a Digital Design Engineer II in Burlingame, CA to join our core engineering team. You will integrate low-speed peripheral IPs (I3C/I2C/SPI/UART) into the SoC, manage IO cells, and develop glue logic and test tooling for RTL-to-GDS workflows.

The role requires 4+ years of hands-on experience with IO mux architecture, UPF low-power flows, and SystemVerilog verification, with a focus on robust subsystem integration.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering, Computer Science, or equivalent experience.
• 4+ years as a Digital Design Engineer with SoC/subsystem integration experience.
• Hands-on integration with I3C, I2C, SPI/QSPI/OSPI and UART controllers.

Responsibilities

• Integrate I3C, I2C, SPI/QSPI/OSPI and UART controller IPs into the peripheral subsystem and SoC top.
• Own IO-level integration including pad/IO cell selection and IO mux design.
• Develop glue logic such as bus bridging, register maps, clock/reset generation, and interrupt/DMA routing.
• Support RTL-to-GDS, constraints, synthesis, timing closure and low-power UPF intent.
• Extend Python-based integration tools for IO mux tables and pinmux collateral.
• Support FPGA prototyping, bring-up, validation and test program development.

Skills

Verilog RTL

SystemVerilog

Python scripting

Tcl scripting

UPF flows

UVM/OVM

IO mux

Education

Bachelor's in Electrical/Computer Engineering

Tools

CAN/CAN-FD

Job description

Job#: 3051914Job Description:Core Engineering - Design Engineer IILocation: Burlingame, California (On-site 3 days preferred, remote possible)' COMPENSATION: $113 - $123 HOURLY

Role Overview

This position is for a digital design engineer to integrate the low-speed peripheral subsystem, including I3C, I2C, SPI/QSPI/OSPI, and UART controllers. The role involves managing the IO cells, pad ring connectivity, and IO multiplexing that these peripherals depend on.

Key Responsibilities

• Integrate I3C, I2C, SPI/QSPI/OSPI, and UART controller IPs into the peripheral subsystem and System-on-Chip (SoC) top.
• Own IO-level integration, including pad/IO cell selection, IO mux design, and management of pad state during reset/power modes.
• Develop glue and control logic such as bus bridging (APB/AHB/AXI), register maps, clock/reset generation, and interrupt/DMA request routing.
• Contribute to subsystem microarchitecture and top-level RTL, and support the verification plan.
• Extend and maintain Python-based integration and generation tooling for IO mux tables and pinmux collateral.
• Support the RTL-to-GDS process, including constraints, synthesis, timing closure, and low-power (UPF) intent.
• Support FPGA prototyping, bring-up, validation, and test program development.

Required Qualifications

Education: A Bachelor of Science in Electrical/Computer Engineering, Computer Science, or equivalent experience is required.

Experience: 4+ years as a Digital Design Engineer, with ownership of SoC/subsystem integration. Hands-on integration experience with I3C, I2C, SPI/QSPI/OSPI, and UART controllers is necessary.

Technical Skills

• Strong Verilog/SystemVerilog RTL coding and digital microarchitecture definition skills.
• Python scripting is required for integration tools.
• Practical understanding of IOs/pads used for peripherals and IO mux architecture.
• Tcl scripting and familiarity with synthesis and static timing.
• Experience with UPF-based simulation/low-power flows.
• Exposure to SystemVerilog UVM/OVM.
• Familiarity with AI-assisted code and IO system operations.

Preferred Qualifications

• Experience with CAN / CAN-FD protocol and CAN controller integration.
• Knowledge of I3C advanced features such as in-band interrupts, hot-join, and dynamic address assignment.
• Experience with sensor-hub or MCU subsystem integration.
• Experience with DFT/testability, Power-Aware GLS, and FPGA prototyping.
• Exposure to PCIe, USB, or MIPI protocols.
• A Master of Science in Electrical Engineering or Computer Science (MSEE/CS).

Pursuant to the California Fair Chance Act, Los Angeles County Fair Chance Ordinance for Employers, Los Angeles Fair Chance Initiative for Hiring Ordinance, and San Francisco Fair Chance Ordinance, qualified applicants will be considered for assignment with arrest and conviction records. Criminal history may have a direct, adverse, and negative relationship with some of the material job duties of this position. These include the duties and responsibilities listed above, as well as the abilities to adhere to company policies, exercise sound judgment, effectively manage stress and work safely and respectfully with others, exhibit trustworthiness, meet client expectations, standards, and accompanying requirements, and safeguard business operations and company reputation.

Everforth Apex Benefits Overview: Everforth Apex offers a range of supplemental benefits, including medical, dental, vision, life, disability, and other insurance plans that offer an optional layer of financial protection.

We offer an ESPP (employee stock purchase program) and a 401K program which allows you to contribute typically within 30 days of starting, with a company match after 12 months of tenure.

Everforth Apex also offers a HSA (Health Savings Account on the HDHP plan), a SupportLinc Employee Assistance Program (EAP) with up to 8 free counseling sessions, a corporate discount savings program and other discounts.

In terms of professional development, Everforth Apex hosts an on-demand training program, provides access to certification prep and a library of technical and leadership courses/books/seminars once you have 6+ months of tenure, and certification discounts and other perks to associations that include CompTIA and IIBA.

Everforth Apex has a dedicated customer service team for our Consultants that can address questions around benefits and other resources, as well as a certified Career Coach.

You can access a full list of our benefits, programs, support teams and resources within our ‘Welcome Packet’ as well, which an Everforth Apex team member can provide.

Everforth Apex Systems is an equal opportunity employer. We do not discriminate or allow discrimination on the basis of race, color, religion, creed, sex (including pregnancy, childbirth, breastfeeding, or related medical conditions), age, sexual orientation, gender identity, national origin, ancestry, citizenship, genetic information, registered domestic partner status, marital status, disability, status as a crime victim, protected veteran status, political affiliation, union membership, or any other characteristic protected by law. Everforth Apex will consider qualified applicants with criminal histories in a manner consistent with the requirements of applicable law.

If you require an accommodation under the Americans with Disabilities Act to participate in an interview with a virtual recruiter or to use our website for a search or application, please contact our Benefits Department at [email protected] or 804-523-8228. Please note that this contact information is strictly to be used for medical ADA accommodations and that no other inquiries will be answered.

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Everforth Apex Systems is part of the Commercial Segment of Everforth, Inc.

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