Design Engineer II — IO/SoC Integration (Hybrid/Remote)

US Tech Solutions; Burlingame (CA); Hybrid; USD 140,000 - 312,000; Full time

Benefits offered by this job

Hybrid/Remote work

Job summary

US Tech Solutions in Burlingame, CA seeks a Contract Digital Design Engineer to integrate low-speed peripheral subsystems (I3C/I2C, SPI/QSPI/OSPI, UART) into an SoC. You will own IO-level integration, IO mux design, and programability, including pad state during reset and power modes.

You will develop glue logic, bus bridges, clock/reset generation, and contribute to μArchitecture and RTL verification. This 8-month contract requires strong Verilog/SystemVerilog, Python scripting, and

Qualifications

• 4+ years as a Digital Design Engineer with SoC/subsystem integration ownership.
• Hands-on integration of I3C, I2C, SPI/QSPI/OSPI and UART controllers.
• Strong Verilog/SystemVerilog RTL coding and μArchitecture definition.
• Python scripting for integration tooling and familiarity with Tcl-based flows.
• UPF-based low-power flows and SystemVerilog UVM/OVM exposure.
• BS in Electrical/Computer Engineering or equivalent.

Responsibilities

• Integrate I3C, I2C, SPI/QSPI/OSPI and UART controller IPs into the peripheral subsystem and SoC top.
• Own IO-level integration: pad/IO cell selection, IO mux design, programmability and pull-ups.
• Develop glue logic: bus bridging, register maps, clock/reset generation, CDC and DMA routing.
• Contribute to μArchitecture, RTL verification plans, and verification support.
• Extend Python-based tooling for IO mux tables, pinmux collateral and connectivity.

Skills

Digital design

Verilog/SystemVerilog

Python scripting

IO/pads knowledge

SoC integration

UVM/OVM exposure

Education

Bachelor's degree

Tools

Python

Tcl

Synthesis tools

Job description

US Tech Solutions in Burlingame, CA seeks a Contract Digital Design Engineer to integrate low-speed peripheral subsystems (I3C/I2C, SPI/QSPI/OSPI, UART) into an SoC. You will own IO-level integration, IO mux design, and programability, including pad state during reset and power modes.

You will develop glue logic, bus bridges, clock/reset generation, and contribute to μArchitecture and RTL verification. This 8-month contract requires strong Verilog/SystemVerilog, Python scripting, and