Design Engineer II: SoC I/O & IP Integration (Hybrid)

US Tech Solutions, Inc.; Burlingame (CA); Hybrid; USD 110,000 - 160,000; Part time

Job summary

US Tech Solutions, a global staffing firm, seeks a Digital Design Engineer for an 8‑month contract in Burlingame, CA, with hybrid/remote options. You will own subsystems integration, including I3C/I2C/SPI/UART controllers, IO pads, and IO muxes.

Responsibilities include glue logic, bus bridging, IRQ/DMA routing, and micro-architecture contributions while using Python-based tooling for IO mux and register generation. Prior UPF and UVM experience is valued.

Qualifications

• 4+ years as a Digital Design Engineer with SoC/subsystem integration ownership
• Hands-on integration of I3C, I2C, SPI/QSPI/OSPI and UART controllers
• Strong Verilog/SystemVerilog RTL coding and digital microarchitecture definition
• Python scripting is required; Tcl familiarity with integration tools
• Experience with UPF low-power flows and SystemVerilog UVM/OVM exposure
• BS in Electrical/Computer Engineering or Computer Science or equivalent
• Familiarity with AI-assisted coding
• IO system/pad/IO mux architecture knowledge

Responsibilities

• Integrate I3C, I2C, SPI/QSPI/OSPI and UART controller IPs into the peripheral subsystem and SoC top
• Own IO-level integration: pad/IO cell selection and configuration, IO mux design and programmability
• Develop glue and control logic: bus bridging (APB/AHB/AXI), register maps, clock and reset generation/gating
• Interrupt and DMA routing, CDC
• Contribute to subsystem micro-architecture and top-level RTL; drive integration, verification plan, and verification support
• Extend and maintain Python-based integration/generation tooling (IO mux tables, pinmux collateral, connectivity and register generation)
• Support RTL-to-GDS: constraints, synthesis, timing closure, UPF intent for peripheral/IO domain
• Support FPGA prototyping, bring-up/validation, test program development, and chip life to production maturity

Skills

Verilog/SystemVerilog

Python scripting

SoC integration

IO/pads knowledge

UPF low-power flows

UVM/OVM exposure

AI-assisted coding

IO mux/pinmux

Education

Bachelor's degree in Engineering

Job description

US Tech Solutions, a global staffing firm, seeks a Digital Design Engineer for an 8‑month contract in Burlingame, CA, with hybrid/remote options. You will own subsystems integration, including I3C/I2C/SPI/UART controllers, IO pads, and IO muxes.

Responsibilities include glue logic, bus bridging, IRQ/DMA routing, and micro-architecture contributions while using Python-based tooling for IO mux and register generation. Prior UPF and UVM experience is valued.