SoC IO & Peripheral Design Engineer II

US Tech Solutions; Burlingame (CA); Hybrid; USD 110,000 - 130,000; Full time

Benefits offered by this job

Hybrid/Remote work options

Job summary

US Tech Solutions is seeking a Contract Digital Design Engineer to integrate low-speed peripheral subsystems (I3C, I2C, SPI/QSPI/OSPI, UART) with IO cells, pad ring connectivity and IO multiplexing. You will own IO-level integration and develop glue logic for bus bridging and register maps.

Responsibilities include RTL-driven design, verification planning, Python tooling extension, and FPGA bring-up through production readiness. 8‑month contract in Burlingame, CA with hybrid/remote options.

Qualifications

• 4+ years as a Digital Design Engineer with SoC/subsystem integration ownership
• Hands‑on integration of I3C, I2C, SPI/QSPI/OSPI and UART controllers
• Practical understanding of IOs/pads used for peripherals and IO mux architecture
• Strong Verilog/SystemVerilog RTL coding; digital μArchitecture definition
• Python scripting — integration tools are Python‑based; Tcl scripting familiarity
• SystemVerilog UVM/OVM exposure
• BS in Electrical/Computer Engineering or Computer Science, or equivalent experience
• Familiarity with AI assisted code
• IO system operations experience

Responsibilities

• Integrate I3C, I2C, SPI/QSPI/OSPI and UART controller IPs into the peripheral subsystem and SoC top
• Own IO-level integration: pad/IO cell selection and configuration, IO mux design and programmability, pull-up/pull-down, drive strength, open-drain vs. push-pull, bidirectional/tri-state control, retention and pad state during reset/power modes
• Develop glue and control logic: bus bridging (APB/AHB/AXI), register maps, clock and reset generation/gating, interrupt and DMA request routing, CDC
• Contribute to subsystem μArchitecture and top-level RTL; drive integration, verification plan development and verification support; apply Design-for-Verification concepts
• Extend and maintain our Python-based integration/generation tooling (IO mux tables, pinmux collateral, connectivity and register generation)
• Support RTL-to-GDS: constraints, synthesis, timing closure, low-power (UPF) intent for the peripheral/IO domain
• Support FPGA prototyping, bring-up/validation, test program development and chip life to production maturity

Skills

Verilog/SystemVerilog

Python scripting

Digital design

SoC integration

UPF low-power

UVM/OVM familiarity

Tcl scripting

IO/pads understanding

Education

BS in Electrical/Computer Engineering or Computer Science

Tools

Synthesis tools

Job description

US Tech Solutions is seeking a Contract Digital Design Engineer to integrate low-speed peripheral subsystems (I3C, I2C, SPI/QSPI/OSPI, UART) with IO cells, pad ring connectivity and IO multiplexing. You will own IO-level integration and develop glue logic for bus bridging and register maps.

Responsibilities include RTL-driven design, verification planning, Python tooling extension, and FPGA bring-up through production readiness. 8‑month contract in Burlingame, CA with hybrid/remote options.