Senior Verification Engineer, Multimedia & AI/ML SoC

Google; Mountain View (CA); On-site; USD 163,000 - 236,000; Full time

Job summary

Google’s hardware team in Mountain View seeks a seasoned verification engineer to advance design verification across IPs and subsystems. You will develop and maintain testbenches, create constrained-random environments, and drive coverage-driven validation for high-performance silicon.

Ideal candidates hold a Bachelor's in EE/CS with 8 years of experience in verification languages and protocols. Collaboration across architecture, software, and design is essential for successful tape-out and

Qualifications

• Bachelor's degree in electrical engineering or computer science, or equivalent practical experience.
• 8 years of experience with verification methodologies and languages (e.g., UVM and SystemVerilog).
• Experience with interconnect protocols (e.g., AXI, APB, ACE).
• Experience developing and maintaining verification testbenches, test cases, and test environments.

Responsibilities

• Learn more about benefits at Google .
• Work with designers, architects, and other stakeholders to come up with detailed test plans, dependencies, and deliverables, while representing DV status throughout the development process.
• Plan the verification of multimedia design blocks at subsystem level by understanding the design specification, and interacting with architecture and design engineers to identify important verification scenarios.
• Work with architecture, software, design, and back-end implementation stakeholders to make technical decisions.
• Create and enhance constrained-random verification environments using system verilog and UVM. Identify and implement improvements to the verification methodologies.
• Identify verification gaps and demonstrate advancement towards tape-out through comprehensive coverage metrics. Debug tests with design engineers to deliver functionally correct design blocks.

Skills

Verification methodologies

UVM

SystemVerilog

Interconnect protocols

Testbenches development

Automation scripting

Education

Bachelor's degree in EE or CS

Tools

UVM tooling

SystemVerilog

Job description

Google’s hardware team in Mountain View seeks a seasoned verification engineer to advance design verification across IPs and subsystems. You will develop and maintain testbenches, create constrained-random environments, and drive coverage-driven validation for high-performance silicon.

Ideal candidates hold a Bachelor's in EE/CS with 8 years of experience in verification languages and protocols. Collaboration across architecture, software, and design is essential for successful tape-out and