Design Verification Engineer, Silicon

Google; Mountain View (CA); On-site; USD 138,000 - 197,000; Full time

Job summary

Google is seeking a verification engineer to contribute to the verification of next-generation SoCs at Mountain View, CA. The role emphasizes SystemVerilog/UVM and formal verification to ensure bug-free silicon.

You will plan verification strategies, build constrained-random environments, and drive coverage closure, collaborating with design and software teams.

Individual pay details vary, with a competitive package including base salary, bonus target, and equity.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
• 4 years of experience with verification methodologies and languages, including SystemVerilog and UVM.
• Experience with interconnect protocols such as AXI, APB, and ACE.
• Experience building and maintaining verification test benches, test environments.

Responsibilities

• Plan verification strategies for complex digital design blocks by thoroughly understanding design specifications and collaborating with design engineers to identify critical verification scenarios.
• Build constrained-random verification environments utilizing SystemVerilog and Universal Verification Methodology (UVM).
• Define and implement comprehensive coverage metrics targeting stimulus and corner cases.
• Debug test failures alongside design engineers to ensure functionally correct design blocks.
• Achieve coverage closure to identify verification gaps and demonstrate progress toward tape-out.

Skills

SystemVerilog

UVM

Verification methodologies

Test benches

AXI

APB

ACE

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science (emphasis on computer architecture)

Tools

AXI

APB

ACE

Job description

In most instances, this position requires in-person interviews as part of the hiring process.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
• 4 years of experience working with verification methodologies and languages, including SystemVerilog and UVM.
• Experience with interconnect protocols such as AXI, APB, and ACE.
• Experience building and maintaining verification test benches, test cases, and test environments.

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience managing the full verification life cycle, from initial test planning through coverage closure.
• Expertise in advanced verification methodologies and techniques (including UVM, formal verification, and UPF-based power simulations) to ensure bug-free silicon in complex SoCs.
• Strong problem-solving and communication skills, with the ability to collaborate effectively in a team setting.

About the job

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $138000 - $197000 (USD) + 15% bonus target + equity + benefits

Responsibilities

• Plan verification strategies for complex digital design blocks by thoroughly understanding design specifications and collaborating with design engineers to identify critical verification scenarios.
• Build constrained-random verification environments utilizing SystemVerilog and Universal Verification Methodology (UVM).
• Define and implement comprehensive coverage metrics targeting stimulus and corner cases.
• Debug test failures alongside design engineers to ensure functionally correct design blocks.
• Achieve coverage closure to identify verification gaps and demonstrate progress toward tape-out.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .