Senior Verification Engineer for SoCs (SystemVerilog/UVM)

Google; Mountain View (CA); On-site; USD 138,000 - 197,000; Full time

Job summary

Google is seeking a verification engineer to contribute to the verification of next-generation SoCs at Mountain View, CA. The role emphasizes SystemVerilog/UVM and formal verification to ensure bug-free silicon.

You will plan verification strategies, build constrained-random environments, and drive coverage closure, collaborating with design and software teams.

Individual pay details vary, with a competitive package including base salary, bonus target, and equity.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent practical experience.
• 4 years of experience with verification methodologies and languages, including SystemVerilog and UVM.
• Experience with interconnect protocols such as AXI, APB, and ACE.
• Experience building and maintaining verification test benches, test environments.

Responsibilities

• Plan verification strategies for complex digital design blocks by thoroughly understanding design specifications and collaborating with design engineers to identify critical verification scenarios.
• Build constrained-random verification environments utilizing SystemVerilog and Universal Verification Methodology (UVM).
• Define and implement comprehensive coverage metrics targeting stimulus and corner cases.
• Debug test failures alongside design engineers to ensure functionally correct design blocks.
• Achieve coverage closure to identify verification gaps and demonstrate progress toward tape-out.

Skills

SystemVerilog

UVM

Verification methodologies

Test benches

AXI

APB

ACE

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science (emphasis on computer architecture)

Tools

AXI

APB

ACE

Job description

Google is seeking a verification engineer to contribute to the verification of next-generation SoCs at Mountain View, CA. The role emphasizes SystemVerilog/UVM and formal verification to ensure bug-free silicon.

You will plan verification strategies, build constrained-random environments, and drive coverage closure, collaborating with design and software teams.

Individual pay details vary, with a competitive package including base salary, bonus target, and equity.