Silicon Design Validation Engineer for FPGA IPs

Lattice Semiconductor; San Jose (CA); Presencial; USD 102 000 - 170 000; Tempo integral

Resumo da oferta

Lattice Semiconductor in San Jose, CA seeks a Silicon Design Validation Engineer to learn and verify FPGA IP blocks, including SerDes and DDR interfaces, across planning to production.

You will develop validation plans, write RTL test logic, run bench tests, and analyze results with statistical tools. This role offers exposure to cutting-edge hardware, software tools, and cross-functional teamwork.

Qualificações

• 2+ years of experience in silicon design validation or related field.
• Electrical Engineering degree with interest in silicon design.
• Expertise in high-speed Serdes Interface tests (PCIe/Ethernet/SDI/CoaXpress/JESD204).
• Expertise in high-speed board design and signal integrity evaluation.
• Verilog/VHDL knowledge and FPGA development experience.
• Proficient in Python or Perl for test automation.
• Familiar with JMP and R for data analysis.
• Experience with lab equipment like BERT, VNA, oscilloscopes.
• Strong communication and teamwork.

Responsabilidades

• Develop validation plans for IPs and bench hardware, from planning to release.
• Create test RTL to validate IPs from silicon arrival to production release.
• Drive silicon bring-up, validation and debugging for IPs.
• Characterize data sheet parameters and analyze results.
• Coordinate with design, verification, manufacturing and quality teams.
• Support customer issues after product release.

Conhecimentos

2+ years of experience

Electrical Engineering degree

Verilog/VHDL

FPGA development tools

Python/Perl

High-speed SerDes testing

Signal integrity analysis

Data analysis with JMP/R

Lab equipment (BERT, VNA, oscilloscope

Cross-functional collaboration

Formação académica

Electrical Engineering degree

Ferramentas

FPGA development tools

JMP

R

Descrição da oferta de emprego

Lattice Semiconductor in San Jose, CA seeks a Silicon Design Validation Engineer to learn and verify FPGA IP blocks, including SerDes and DDR interfaces, across planning to production.

You will develop validation plans, write RTL test logic, run bench tests, and analyze results with statistical tools. This role offers exposure to cutting-edge hardware, software tools, and cross-functional teamwork.