Senior IP & FPGA Integration Engineer

Lattice Semiconductor; San Jose (CA); On-site; USD 221,000 - 290,000; Full time

Benefits offered by this job

Healthcare

Retirement plan

Paid time off

Job summary

Lattice Semiconductor, with a strong presence in San Jose, seeks a senior engineer to lead IP/sector integration for FPGA platforms. You will drive RTL/debug flows, SDC/STA, and DFT integration, coordinating across IP, product engineering, and test teams to ensure robust sign-off.

The ideal candidate has 15+ years in ASIC/SoC/FPGA, strong Verilog/SystemVerilog expertise, and experience with Cadence Virtuoso and SPICE simulations.

Qualifications

• 15+ years of experience in ASIC, SoC, or FPGA design and product development.
• Expertise in Verilog and SystemVerilog is required.
• Experience in FPGA/CPLD design and integration is a plus.
• Strong background in digital design flow, RTL coding, lint, synthesis, and DFT/ATPG.

Responsibilities

• Integrate IP blocks into FPGA platforms and deliver models, views, and collateral.
• Own sector-level design constraints and SDC generation for STA.
• Run digital implementation flow: RTL updates, synthesis, LEC, STA, and DFT integration.
• Support custom/physical design tasks and tapeout readiness.
• Coordinate with DFT, IP, and product teams; manage releases and issue tracking.
• Run DV regressions and sign-off checks for each sector release.
• Collaborate to integrate IP-level power data into full-chip models and budgets.
• Review SPICE-level simulations and Power results across corners.

Skills

Verilog

SystemVerilog

FPGA design

Digital design flow

RTL coding

Scripting: Python/Tcl

Communication

Education

BS or MS in Electronics/Computer/Electrical Engineering

Tools

Cadence Virtuoso

SPICE

Job description

Lattice Semiconductor, with a strong presence in San Jose, seeks a senior engineer to lead IP/sector integration for FPGA platforms. You will drive RTL/debug flows, SDC/STA, and DFT integration, coordinating across IP, product engineering, and test teams to ensure robust sign-off.

The ideal candidate has 15+ years in ASIC/SoC/FPGA, strong Verilog/SystemVerilog expertise, and experience with Cadence Virtuoso and SPICE simulations.