Senior Staff FPGA & IP Integration Engineer

Lattice Semiconductor Corp.; San Jose, Northern (CA, KY); Hybrid; USD 221,000 - 320,000; Full time

Benefits offered by this job

Healthcare and retirement plans

Equity

Paid time off

Job summary

Lattice Semiconductor is seeking a Senior Staff Integration Design Engineer in San Jose to drive IP integration, sector-level design, and tapeout-ready design flows. You will own the sector constraints, coordinate with DFT and IP teams, and ensure robust power data integration into full-chip models.

The role demands deep Verilog/SystemVerilog expertise, extensive FPGA/ASIC experience, and leadership across cross-functional teams.

Qualifications

• BS or MS in Electronics/Computer/Electrical Engineering.
• 15+ years of experience in ASIC, SoC, or FPGA design and product development.
• Expert in Verilog and SystemVerilog, RTL coding and verification.
• Experience in FPGA/CPLD design and integration is a plus.
• Experience with DFT flow and ATPG generation.

Responsibilities

• Integrate IP blocks including DDR PHY into sector and full-chip views using digital and custom design flows.
• Maintain sector-level design constraints (SDC) and reconcile clock frequency across IP sources.
• Run and maintain the digital implementation flow: RTL updates, synthesis, LEC, STA, DFT integration.
• Support custom/physical design tasks, including parasitic extraction and clock- critical routing reviews.
• Coordinate with IP Design, Product Engineering, and Test teams to integrate power data into full-chip models.
• Review SPICE-level simulations and correlate with silicon bench data.

Skills

Verilog/SystemVerilog

FPGA/CPLD design

Digital design flow

RTL coding & verification

DFT/ATPG

Scripting (Python/TCL/Shell)

JIRA

Power/thermal modeling

Education

BS or MS in Electronics/Computer/Electrical Engineering

Tools

Cadence Virtuoso

SPICE simulations

SPICE/Verilog simulators

Job description

Lattice Semiconductor is seeking a Senior Staff Integration Design Engineer in San Jose to drive IP integration, sector-level design, and tapeout-ready design flows. You will own the sector constraints, coordinate with DFT and IP teams, and ensure robust power data integration into full-chip models.

The role demands deep Verilog/SystemVerilog expertise, extensive FPGA/ASIC experience, and leadership across cross-functional teams.