Senior Silicon Validation Engineer FPGA IP & Testing

Lattice Semiconductor; San Jose (CA); Vor Ort; USD 199.000 - 243.000; Vollzeit

Zusammenfassung

Lattice Semiconductor is seeking a seasoned Silicon Design Validation Engineer to drive IP validation from silicon arrival to production release in a fast-paced environment. You will work with SerDes, memory interfaces, and IP blocks, developing robust validation plans and RTL test logic while collaborating across design, verification, and manufacturing teams.

The role demands deep expertise in high-speed design, Verilog/VHDL, FPGA development tools, and automation using Python or similar

Qualifikationen

• Eight plus years of experience in silicon design validation.
• Strong expertise in high-speed SerDes interface characterization and protocol testing (PCIe, Ethernet, USB, HDMI, etc.).
• Experience with Verilog/VHDL and FPGA development tools; proficient in test automation with Python or Perl.

Aufgaben

• Validate and characterize IP blocks from silicon arrival to release.
• Develop validation plans and bench tests for IP blocks and boards.
• Create test logic RTL to validate IP functionality and performance.

Kenntnisse

High Speed Serdes

PCIe/Networking testing

Signal integrity

Verilog/VHDL

FPGA development tools

Python

Lab equipment

Ausbildung

Electrical Engineering degree

Tools

FPGA development tools

Jobbeschreibung

Lattice Semiconductor is seeking a seasoned Silicon Design Validation Engineer to drive IP validation from silicon arrival to production release in a fast-paced environment. You will work with SerDes, memory interfaces, and IP blocks, developing robust validation plans and RTL test logic while collaborating across design, verification, and manufacturing teams.

The role demands deep expertise in high-speed design, Verilog/VHDL, FPGA development tools, and automation using Python or similar