FPGA Design Engineer for AI Silicon & Validation

Digitailor; New York (NY); On-site; USD 140,000 - 210,000; Full time

Job summary

Normal Computing is seeking an FPGA Design Engineer to bridge RTL and physical silicon, bringing AI hardware concepts to life on FPGA platforms for pre-silicon validation and early software development.

You will own the FPGA lifecycle, select hardware, implement complex RTL, debug in the lab, and build the test infrastructure with our silicon, EDA, and research teams. Strong SystemVerilog/VHDL and PCIe experience are required.

Qualifications

• Proven industry experience taking FPGA designs RTL to hardware.
• Expert SystemVerilog and/or VHDL for synthesis and timing closure.
• Hands-on PCIe, AXI, SPI, UART, JTAG interfaces.

Responsibilities

• Lead FPGA platform ownership from selection to bring-up.
• Implement and debug RTL on FPGA targets for pre-silicon validation.
• Integrate in-house designs with vendor IP and AMD/Xilinx ecosystem.
• Develop software layer (Python/C++) for hardware abstraction and test automation.
• Perform lab debugging with oscilloscopes, logic analyzers, and BER measurements.

Skills

FPGA design

SystemVerilog

VHDL

PCIe

Python

C++

Tools

Vivado

HAPS/VCU118

Job description

Normal Computing is seeking an FPGA Design Engineer to bridge RTL and physical silicon, bringing AI hardware concepts to life on FPGA platforms for pre-silicon validation and early software development.

You will own the FPGA lifecycle, select hardware, implement complex RTL, debug in the lab, and build the test infrastructure with our silicon, EDA, and research teams. Strong SystemVerilog/VHDL and PCIe experience are required.