FPGA Design Engineer: RTL-to-Silicon Validation

Normal Computing Corporation; New York (NY); On-site; USD 120,000 - 170,000; Full time

Job summary

Normal Computing is an applied AI company building foundational hardware and software for the semiconductor industry. We’re looking for an FPGA Design Engineer to bridge RTL and physical silicon, enabling pre-silicon validation and early software development on FPGA platforms.

You will own FPGA platform bring-up, RTL adaptation, IP integration, high-speed interfaces (PCIe), and post-silicon validation. Collaborate with silicon, EDA, and research teams in a fast-paced startup environment.

Qualifications

• Proven industry experience taking FPGA designs from RTL through timing closure to validated hardware.
• Expert-level SystemVerilog and/or VHDL for synthesis with Xilinx Vivado proficiency.
• Hands-on experience implementing and debugging PCIe, AXI/AHB, SPI, UART, JTAG interfaces.
• Strong Python for automation, test, and build tooling.
• Strong board-level bring-up and lab debugging skills on real hardware.
• Startup mindset: work independently and solve cross-domain hardware/software problems.

Responsibilities

• FPGA Platform Ownership: lead FPGA prototyping platform selection and bring-up.
• RTL Implementation: adapt ASIC RTL onto FPGA targets with timing closure.
• IP Integration: integrate in-house designs with vendor IP in Vivado.
• High-Speed Interfaces: design and validate PCIe and other high-speed I/O.
• Post-Silicon Validation: build FPGA-based testers for bring-up and characterization.
• Hardware-Software Stack: develop Python/C++ layer and regression flows.
• Lab Debug: root-cause timing and functional issues with dedicated test equipment.

Skills

FPGA design

SystemVerilog/VHDL

Python

Lab debugging

PCIe interfaces

Xilinx Vivado

Tools

Vivado

Oscilloscopes

Logic Analyzers

Job description

Normal Computing is an applied AI company building foundational hardware and software for the semiconductor industry. We’re looking for an FPGA Design Engineer to bridge RTL and physical silicon, enabling pre-silicon validation and early software development on FPGA platforms.

You will own FPGA platform bring-up, RTL adaptation, IP integration, high-speed interfaces (PCIe), and post-silicon validation. Collaborate with silicon, EDA, and research teams in a fast-paced startup environment.