Silicon Bring-Up & Validation Senior Engineer – Next-Gen FPGA

Lattice Semiconductor; San Jose (CA); On-site; USD 140,000 - 210,000; Full time

Benefits offered by this job

Competitive compensation

Equity

Benefits

Collaborative culture

Job summary

Lattice Semiconductor in San Jose, CA is seeking a hands-on validation engineer to drive board-level bring-up and FPGA IP validation across SERDES, DDR, MIPI, and more. You will develop validation plans and write RTL/test scripts to move silicon from arrival to production.

You bring 5+ years in silicon or post-silicon validation, an Electrical Engineering degree, strong signal integrity skills, Verilog/VHDL proficiency, and Python/Perl scripting.

Qualifications

• 5+ years in silicon or post-silicon validation.
• Degree in Electrical Engineering or related field.
• Hands-on high-speed interface characterization (PCIe, Ethernet, MIPI, USB, etc.).
• Proficiency in Verilog/VHDL and FPGA development tools.
• Python or Perl scripting for test automation.
• Experience with bench equipment (BERT, VNA, Oscilloscopes).

Responsibilities

• Lead board-level bring-up and validation of FPGA IPs — SERDES, DDR, DPHY, PCIe, MIPI and more.
• Develop validation and characterization plans from silicon arrival through production release.
• Write test logic RTL and automation scripts to drive validation coverage.
• Characterize datasheet parameters and analyze data with tools like JMP or R.
• Debug silicon issues across design, verification, manufacturing and test teams.
• Support customer escalations post-release as needed.

Skills

silicon validation

FPGA development tools

Verilog/VHDL

Python/Perl scripting

high-speed interface

signal integrity

Education

Electrical Engineering degree

Tools

JMP

R

FPGA toolchains

Job description

You'll be at the front line of silicon — validating and characterizing the building blocks of Lattice's next-generation FPGAs from the moment they arrive off the fab line. This is hands-on, high-stakes work: board-level bring-up, IP characterization, debug, and driving silicon from first power-on to production release.

If you thrive in a lab environment and want your fingerprints on cutting-edge programmable silicon, this is your role.

What You'll Do

• Lead board-level bring-up and validation of FPGA IPs — SERDES (PMA/PCS), DDR (DDR4/DDR5/LPDDR4), DPHY, PLL, DSP, MIPI, Fabric, I/O and more
• Develop validation and characterization plans from silicon arrival through production release
• Write test logic RTL and automation scripts to drive validation coverage
• Characterize datasheet parameters; analyze and present statistical data using tools like JMP or R
• Debug silicon issues across design, verification, manufacturing, and test teams
• Support customer escalations post-release as needed

What You Bring

• 5+ years in silicon or post-silicon validation
• Degree in Electrical Engineering or related field
• Hands-on expertise in high-speed interface characterization — PCIe, Ethernet, MIPI D-PHY, USB, DisplayPort/HDMI, JESD204, SDI/CoaXpress
• Strong signal integrity and high-speed board design skills
• Proficiency in Verilog/VHDL and FPGA development tools
• Scripting in Python or Perl for test automation
• Comfortable with bench equipment — BERT, VNA, Oscilloscopes, Protocol Analyzers
• Strong communicator, self-driven, and sharp on problem-solving

Nice to Have

• Experience with FPGA emulation or prototyping environments
• Familiarity with statistical analysis tools (JMP, R)

Location

San Jose, CA — Onsite, Full-Time

Why Lattice?

We're the low power FPGA leader — solving problems from the Edge to the Cloud across communications, computing, industrial, automotive, and consumer markets. Our validation engineers don't just test silicon; they shape it.

• Competitive compensation | Equity | Benefits | Collaborative culture

Lattice Semiconductor is an equal opportunity employer. We encourage candidates from diverse backgrounds to apply.